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More accurate CHANGELOG
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@ -17,7 +17,9 @@ Yosys 0.8 .. Yosys 0.8-dev
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- Added "rename -src"
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- Added "equiv_opt" pass
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- Added "read_aiger" frontend
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- Added "abc9" pass (experimental, accessible using synth_xilinx -abc9 and synth_ice40 -abc9)
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- Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
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- Added "synth_xilinx -abc9" (experimental)
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- Added "synth_ice40 -abc9" (experimental)
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- "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"
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