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Update CHANGELOG with "synth -abc9"

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Eddie Hung 2019-06-13 09:15:30 -07:00
parent 2052806d33
commit 7f9d2d1825
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CHANGELOG
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@ -20,6 +20,7 @@ Yosys 0.8 .. Yosys 0.8-dev
- Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
- Added "synth_xilinx -abc9" (experimental)
- Added "synth_ice40 -abc9" (experimental)
- Added "synth -abc9" (experimental)
- "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"