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Update CHANGELOG

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Eddie Hung 2019-06-12 16:54:12 -07:00
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CHANGELOG
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@ -17,6 +17,7 @@ Yosys 0.8 .. Yosys 0.8-dev
- Added "rename -src"
- Added "equiv_opt" pass
- Added "read_aiger" frontend
- Added "abc9" pass (experimental, accessible using synth_xilinx -abc9 and synth_ice40 -abc9)
- "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"