Emil J. Tywoniak
20b2e47b42
verilog_location: rename location to Location to avoid conflict with Pass::location
2025-08-08 16:22:54 +02:00
Emil J. Tywoniak
a5228e5bb0
ast: fix import node
2025-08-08 16:15:20 +02:00
Emil J. Tywoniak
90e3579820
ast: remove null_check as dead code
2025-08-08 15:36:43 +02:00
Emil J. Tywoniak
581b9684a2
simplify: std::gcd
2025-08-08 15:36:43 +02:00
Krystine Sherwin
950339b1b0
simplify.cc: Drop unused debug prints
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At least the ones added by this PR. There are some unused debug prints that are *changed* by this PR, but I've left them.
2025-08-08 15:36:43 +02:00
Krystine Sherwin
c12cd1f4fb
frontends/ast: More usage of auto
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For consistency.
2025-08-08 15:36:43 +02:00
Emil J. Tywoniak
2a9102565f
ast, read_verilog: unify location types, reduce filename copying
2025-08-08 15:36:43 +02:00
Emil J. Tywoniak
041599b7d9
neater errors, lost in the sauce of source
2025-08-08 15:36:43 +02:00
Emil J. Tywoniak
a6293df781
ast, read_verilog: refactoring
2025-08-08 15:36:43 +02:00
Emil J. Tywoniak
51fc94cf2d
ast: fix new memory safety bugs from rebase
2025-08-08 15:36:43 +02:00
Emil J. Tywoniak
dfcef88310
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-08-08 15:36:42 +02:00
Rahul Bhagwat
f12055d3e0
rm debug logs
2025-08-06 15:39:36 -04:00
Rahul Bhagwat
7e0157ba2b
fix whitespace issues
2025-08-06 15:32:36 -04:00
Rahul Bhagwat
fe59b6d3db
add safety checks and better name matching
2025-08-04 20:57:43 -04:00
Rahul Bhagwat
761015b23e
add separate module test
2025-08-03 23:48:33 -04:00
Rahul Bhagwat
b776283d79
implement package import
2025-08-03 23:31:54 -04:00
KrystalDelusion
5b8b5292ee
Merge pull request #4959 from YosysHQ/krys/primitive_array_error
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simplify: Skip AST_PRIMITIVE in AST_CELLARRAY
2025-07-21 10:26:00 +12:00
Emil J
378add3723
Merge pull request #5163 from YosysHQ/emil/fix-single-bit-vector-leak
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simplify: fix single_bit_vector memory leak
2025-06-04 17:00:54 +02:00
George Rennie
0fcf5c080d
Merge pull request #5158 from georgerennie/george/task_inout
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read_verilog/astsimplify: copy inout ports in and out of functions/tasks
2025-06-04 14:23:08 +01:00
Emil J. Tywoniak
c37b7b3bf4
simplify: fix single_bit_vector memory leak
2025-06-04 10:32:03 +02:00
George Rennie
45e8ff476e
read_verilog: copy inout ports in and out of functions/tasks
2025-05-31 01:09:03 +01:00
Krystine Sherwin
32ce23458f
read_verilog: Mark struct as custom type
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Being a custom type means that it will be resolved *before* (e.g.) a wire can use it as a type.
2025-05-26 12:19:33 +12:00
Emil J
4b8d42d22c
Merge pull request #5095 from YosysHQ/emil/one-bit-width
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rtlil: enable single-bit vector wires
2025-05-23 15:55:45 +02:00
Emil J. Tywoniak
5e72464a15
rtlil: enable single-bit vector wires
2025-05-12 13:23:29 +02:00
Krystine Sherwin
fe0abb7026
simplify.cc: Fix mem leak
2025-05-10 17:10:47 +12:00
Emil J. Tywoniak
bdc2597f79
simplify: fix struct wiretype attr memory leak
2025-04-25 01:00:08 +02:00
Krystine Sherwin
0a1c664f02
simplify: Skip AST_PRIMITIVE in AST_CELLARRAY
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Otherwise the `AST_PRIMITIVE` simplifies to the corresponding function and is no longer caught by the check for `AST_PRIMITIVE`s, raising an assertion error instead of an input error.
Add bug4785.ys to tests/verilog to demonstrate.
2025-03-25 12:15:54 +13:00
KrystalDelusion
cf52cf3009
nowrshmsk: Check for stride==0
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log2(0) returns -inf, which gives undefined behaviour when casting to an int. So catch the case when it's 0 just set the width to 0.
2025-01-31 12:15:53 +13:00
Krystine Sherwin
1de5d98ae2
Reduce comparisons of size_t and int
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`Const::size()` returns int, so change iterators that use it to `auto` instead of `size_t`.
For cases where size is being explicitly cast to `int`, use the wrapper that we already have instead: `Yosys::GetSize()`.
2024-11-29 12:53:29 +13:00
Emil J. Tywoniak
785bd44da7
rtlil: represent Const strings as std::string
2024-10-14 06:28:12 +02:00
rherveille
ce7db661a8
Added cast to type support ( #4284 )
2024-09-29 17:03:01 -04:00
Catherine
a5441bc00c
fmt: FmtPart::{STRING→LITERAL},{CHARACTER→STRING}.
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Before this commit, the `STRING` variant inserted a literal string;
the `CHARACTER` variant inserted a string. This commit renames them
to `LITERAL` and `STRING` respectively.
2024-04-02 12:13:22 +02:00
Martin Povišer
b16f4900fd
ast/simplify: Interpret hdlname w/o expecting backslash
2024-02-13 21:38:41 +01:00
Dag Lem
f09ea16bd1
Resolve struct member multiple dimensions defined in stages with typedef
2024-02-11 11:26:52 -05:00
Dag Lem
03f35c3def
Resolve multiple dimensions defined in stages with typedef
2024-02-11 11:26:52 -05:00
Dag Lem
e0d3977e19
Add support for $dimensions and $unpacked_dimensions
2024-02-11 11:26:52 -05:00
Dag Lem
2125357e76
Add support for $increment
2024-02-11 11:26:52 -05:00
Dag Lem
39fea32c6e
Add support for packed multidimensional arrays
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* Generalization of dimensions metadata (also simplifies $size et al.)
* Parsing and elaboration of multidimensional packed ranges
2024-02-11 11:26:52 -05:00
Catherine
c7bf0e3b8f
Add new $check cell to represent assertions with a message.
2024-02-01 20:10:39 +01:00
Martin Povišer
149bcd88ad
Merge pull request #4026 from uis246/fix-format
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Fix printf formats
2024-01-15 16:04:11 +01:00
uis
5902b2826d
Fix printf formats
2024-01-15 12:07:54 +01:00
Dag Lem
3ed9030eb4
Optionally suppress output from display system tasks in read_verilog
2024-01-11 13:12:53 +01:00
Jannis Harder
510d137996
fmt: Allow non-constant $display calls in initial blocks
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These are useful for formal verification with SBY where they can be used
to display solver chosen `rand const reg` signals and signals derived
from those.
The previous error message for non-constant initial $display statements
is downgraded to a log message. Constant initial $display statements
will be shown both during elaboration and become part of the RTLIL so
that the `sim` output is complete.
2024-01-11 13:01:28 +01:00
Dag Lem
23cd23efc5
Simplify and correct AST for array slice assignment
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Corrects sign extension of the right hand side, and hopefully
makes the code simpler to understand.
Fixes #4064
2024-01-10 21:15:00 +01:00
Dag Lem
1a2b4759e8
Assign from rvalue via temporary register in nowrshmsk CASE
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Avoid repeating complex rvalue expressions for each condition.
2024-01-10 20:40:01 +01:00
Dag Lem
2cab4ff173
Correction and optimization of nowrshmsk
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This makes tests/verilog/dynamic_range_lhs.v pass, after ensuring that
nowrshmsk is actually tested.
Stride is extracted from indexing of two-dimensional packed arrays and
variable slices on the form dst[i*stride +: width] = src, and is used
to optimize the generated CASE block.
Also uses less confusing variable names for indexing of lhs wires.
2024-01-10 20:28:36 +01:00
Dag Lem
1bbea13f80
Correct hierarchical path names for structs and unions
2024-01-04 17:22:07 +01:00
Martin Povišer
8367f06188
ast/simplify: Remove unused in_param code
2023-10-05 22:42:36 -04:00
Jannis Harder
cc843d414f
simplify: Avoid calling fixup_hierarchy_flags on nullptr
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Compiling on GCC hid this bug as it optimized the nullptr call away as
undefined behavior, but running the SBY tests with a clang build hits
this error.
2023-09-29 12:28:50 +02:00
Martin Povišer
a511976b48
ast/simplify: Retire in_lvalue/in_param arguments to simplify
2023-09-26 13:32:15 +02:00
