398 commits

Author	SHA1	Message	Date
Marcus Comstedt	dd562f29e7	Add regression tests for new handling of comments in constants	2020-03-14 11:41:09 +01:00
Miodrag Milanović	faf4ee69de	Merge pull request #1754 from boqwxp/precise_locations ... Set AST node source location in more parser rules.	2020-03-14 11:18:39 +02:00
Miodrag Milanovic	5b73e7c63a	Added back tests for logger	2020-03-13 15:00:18 +01:00
Eddie Hung	3ada82639f	verilog: add test	2020-03-11 06:51:03 -07:00
David Shah	ddcd87b577	Merge pull request #1721 from YosysHQ/dave/tribuf-unused ... deminout: Don't demote inouts with unused bits	2020-03-10 13:51:40 +00:00
David Shah	5cae9c6e16	deminout: Don't demote inouts with unused bits ... Signed-off-by: David Shah <dave@ds0.me>	2020-03-04 18:44:38 +00:00
Claire Wolf	b597f85b13	Merge pull request #1718 from boqwxp/precise_locations ... Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.	2020-03-03 08:38:32 -08:00
Claire Wolf	879124333f	Merge pull request #1519 from YosysHQ/eddie/submod_po ... submod: several bugfixes	2020-03-03 08:19:06 -08:00
Eddie Hung	4f889b2f57	Merge pull request #1724 from YosysHQ/eddie/abc9_specify ... abc9: auto-generate *.lut/*.box files and arrival/required times from specify entries	2020-03-02 12:32:27 -08:00
Eddie Hung	5bba9c3640	ast: fixes #1710; do not generate RTLIL for unreachable ternary	2020-02-27 16:55:55 -08:00
Eddie Hung	f858219c4e	Cleanup tests	2020-02-27 10:17:29 -08:00
Alberto Gonzalez	2c2f092c90	Change attribute search value to specify precise location instead of simple line number.	2020-02-24 01:39:36 +00:00
Eddie Hung	1d401a7991	clean: ignore specify-s inside cells when determining whether to keep	2020-02-19 10:45:10 -08:00
Eddie Hung	d20c1dac73	verilog: ignore ranges too without -specify	2020-02-13 17:58:43 -08:00
Eddie Hung	6b58c1820c	verilog: improve specify support when not in -specify mode	2020-02-13 13:27:15 -08:00
Eddie Hung	2e51dc1856	verilog: ignore '&&&' when not in -specify mode	2020-02-13 13:06:13 -08:00
Eddie Hung	b523ecf2f4	specify: system timing checks to accept min:typ:max triple	2020-02-13 12:42:15 -08:00
Eddie Hung	7cfdf4ffa7	verilog: fix $specify3 check	2020-02-13 12:42:04 -08:00
N. Engelhardt	e069259a53	Merge pull request #1679 from thasti/delay-parsing ... Fix crash on wire declaration with delay	2020-02-13 12:01:27 +01:00
Stefan Biereigel	90c78f1f85	add testcase for #1614	2020-02-03 21:29:54 +01:00
David Shah	ebe1d7d5ab	sv: More tests for wildcard port connections ... Signed-off-by: David Shah <dave@ds0.me>	2020-02-02 16:12:33 +00:00
David Shah	7e741714df	hierarchy: Correct handling of wildcard port connections with default values ... Signed-off-by: David Shah <dave@ds0.me>	2020-02-02 16:12:33 +00:00
David Shah	a210675d71	sv: Add tests for wildcard port connections ... Signed-off-by: David Shah <dave@ds0.me>	2020-02-02 16:12:33 +00:00
David Shah	9f5613100b	Merge pull request #1647 from YosysHQ/dave/sprintf ... ast: Add support for $sformatf system function	2020-02-02 14:53:46 +00:00
Eddie Hung	136842b1ef	Merge branch 'master' into eddie/submod_po	2020-02-01 02:14:19 -08:00
Eddie Hung	d004953772	Add "help -all" and "help -celltypes" sanity test	2020-01-28 18:11:34 -08:00
Eddie Hung	3d9737c1bd	Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor	2020-01-21 16:27:40 -08:00
Eddie Hung	cd8f55a911	write_xaiger: fix for (* keep *) on flop output	2020-01-21 09:43:04 -08:00
David Shah	22c967e35e	ast: Add support for $sformatf system function ... Signed-off-by: David Shah <dave@ds0.me>	2020-01-19 21:20:17 +00:00
Eddie Hung	6a163b5ddd	xilinx_dsp: another typo; move xilinx specific test	2020-01-17 17:07:03 -08:00
Eddie Hung	00964e999d	autoname: add testcase with $-prefix-ed port	2020-01-14 10:13:03 -08:00
Eddie Hung	fc4b8b8991	Remove submod changes	2019-12-30 14:56:14 -08:00
Eddie Hung	1ea1e8e54f	Merge remote-tracking branch 'origin/master' into xaig_dff	2019-12-20 13:56:13 -08:00
Eddie Hung	94f15f023c	Merge remote-tracking branch 'origin/master' into xaig_dff	2019-12-19 10:29:40 -08:00
Eddie Hung	d406f2ffd7	Merge pull request #1569 from YosysHQ/eddie/fix_1531 ... verilog: preserve size of $genval$-s in for loops	2019-12-19 12:21:33 -05:00
N. Engelhardt	abcd82daca	add assert option to scratchpad command	2019-12-16 14:00:21 +01:00
N. Engelhardt	1187e91c2f	add test and make help message more verbose	2019-12-12 20:51:59 +01:00
Eddie Hung	151f7533e8	Add testcase	2019-12-11 16:52:37 -08:00
Eddie Hung	705e520a52	Add a quick testcase for unknown modules as inout	2019-12-09 13:14:46 -08:00
Eddie Hung	c61186dd9d	Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff	2019-11-27 13:24:03 -08:00
Eddie Hung	ff1e357682	Add multiple driver testcase	2019-11-27 13:22:26 -08:00
Eddie Hung	6338615aa1	Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff	2019-11-27 01:02:16 -08:00
Eddie Hung	8c813632b6	Revert "submod to bitty rather bussy, for bussy wires used as input and output" ... This reverts commit cba3073026.	2019-11-27 00:48:22 -08:00
Eddie Hung	6318e3ce6d	Fix wire width	2019-11-26 23:38:49 -08:00
Eddie Hung	dd317c9280	Add testcase where \init is copied	2019-11-25 16:07:35 -08:00
Eddie Hung	b46e636c91	Merge branch 'xaig_dff' of github.com:YosysHQ/yosys into xaig_dff	2019-11-23 08:38:48 -08:00
Eddie Hung	d223e11a72	Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff	2019-11-22 22:28:35 -08:00
Eddie Hung	5cd3d3db0a	Remove redundant flatten	2019-11-22 22:28:10 -08:00
Eddie Hung	08f85e6438	Stray dump	2019-11-22 20:53:48 -08:00
Eddie Hung	2c5dfd802d	Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff	2019-11-22 17:24:45 -08:00