385 commits

Author	SHA1	Message	Date
Clifford Wolf	31755ed1cf	Changed ice40 ICESTORM_CARRYCONST port name	2015-04-16 12:09:14 +02:00
Clifford Wolf	dc30b034f7	Fixed "dff2dffe -direct-match"	2015-04-16 11:47:59 +02:00
Clifford Wolf	3e9e6e1c22	Added simple ice40 dff tests	2015-04-16 11:31:15 +02:00
Clifford Wolf	0d344a23d3	improved ice40 dff cell mapping	2015-04-16 11:30:56 +02:00
Clifford Wolf	4529c56cc6	use "hierarchy -auto-top" in synth_ice40	2015-04-14 13:45:15 +02:00
Clifford Wolf	06ce496f8d	more cells in ice40 cell library	2015-04-14 13:44:43 +02:00
Clifford Wolf	3481f46d1e	Improved xilinx "bram1" test	2015-04-09 17:12:12 +02:00
Clifford Wolf	7319951145	Added memory_bram "make_outreg" feature	2015-04-09 16:08:54 +02:00
Clifford Wolf	229825e1b8	Xilinx DRAMS: RAM64X1D, RAM128X1D	2015-04-09 13:37:07 +02:00
Clifford Wolf	b00cad81d7	Towards DRAM support in Xilinx flow	2015-04-09 08:17:14 +02:00
Clifford Wolf	8520b7fbe0	Added support for initialized xilinx brams	2015-04-06 17:07:10 +02:00
Clifford Wolf	d19866615b	Added Xilinx test case for initialized brams	2015-04-06 13:27:11 +02:00
Clifford Wolf	4389d9306e	Added Xilinx bram black-box modules	2015-04-06 08:44:30 +02:00
Clifford Wolf	95944eb69e	make all vector-size related integer params in $mem sim model signed ... this fixes iverilog crashes such as the following: warning: verinum::as_long() truncated 32 bits to 31, returns 2147483647 draw_net_input.c:711: Error: malloc() ran out of memory.	2015-04-05 17:26:53 +02:00
Clifford Wolf	706631225e	Added $_MUX4_, $_MUX8_, and $_MUX16_ cell types	2015-04-05 09:45:14 +02:00
Clifford Wolf	c52a4cdeed	Added "dffinit", Support for initialized Xilinx DFF	2015-04-04 19:00:15 +02:00
Clifford Wolf	e468d4cc60	Fixes in cmos_cells.v	2015-03-25 09:00:41 +01:00
Clifford Wolf	42d5d94a5d	Added very first version of "synth_ice40"	2015-03-05 20:37:55 +01:00
Clifford Wolf	b005eedf36	Added $assume cell type	2015-02-26 18:04:10 +01:00
Clifford Wolf	4d34d031f9	Added "stat" to "synth" and "synth_xilinx"	2015-02-15 13:25:15 +01:00
Clifford Wolf	881dcd8af9	Added final checks to "synth" and "synth_xilinx"	2015-02-15 13:00:00 +01:00
Clifford Wolf	ec05242c27	Smaller default parameters in $mem simlib model	2015-02-15 00:20:05 +01:00
Clifford Wolf	dcf2e24240	Added $meminit support to "memory" command	2015-02-14 12:55:03 +01:00
Clifford Wolf	910556560f	Added $meminit cell type	2015-02-14 10:23:03 +01:00
Clifford Wolf	04cb947d6a	Added "check" command	2015-02-13 14:34:51 +01:00
Clifford Wolf	d58c3eca3a	Some test related fixes ... (incl. removal of three bad test cases)	2015-02-12 17:45:44 +01:00
Clifford Wolf	853e949c0e	Disabled (unused) Xilinx tristate buffers	2015-02-04 16:33:59 +01:00
Clifford Wolf	bebbf2e5a4	no support for 6-series xilinx devices	2015-02-01 23:06:44 +01:00
Clifford Wolf	3cbfa3815e	Removed old XST-based xilinx examples	2015-02-01 17:10:46 +01:00
Clifford Wolf	816fe6bbe0	Added Xilinx example for Basys3 board	2015-02-01 17:09:34 +01:00
Clifford Wolf	1b159bc955	Added missing ports and parameters to xilinx brams	2015-02-01 15:42:59 +01:00
Clifford Wolf	1df81f92ce	Added "make mklibyosys", some minor API changes	2015-02-01 13:38:46 +01:00
Clifford Wolf	bedd46338f	Added "fsm -encfile"	2015-01-30 22:46:53 +01:00
Clifford Wolf	909a95182b	Fixed xilinx FDSE sim model	2015-01-24 11:03:22 +01:00
Clifford Wolf	e13a45ae61	Added $equiv cell type	2015-01-19 11:55:05 +01:00
Clifford Wolf	d29d26f882	Various cleanups in xilinx techlib	2015-01-18 19:43:54 +01:00
Clifford Wolf	8d295730e5	Refactoring of memory_bram and xilinx brams	2015-01-18 19:05:29 +01:00
Clifford Wolf	279a18c9a3	Added synth_xilinx -retime -flatten	2015-01-17 20:47:18 +01:00
Clifford Wolf	7031231145	Added MUXCY and XORCY support to synth_xilinx	2015-01-17 15:39:54 +01:00
Clifford Wolf	3ed4e34380	Added cells.lib	2015-01-16 15:50:42 +01:00
Clifford Wolf	dff8bd3b2a	Added dff2dffe to synth_xilinx	2015-01-16 15:49:15 +01:00
Clifford Wolf	7bde74cd2a	Added more FF types to xilinx/cells.v	2015-01-16 15:24:54 +01:00
Clifford Wolf	6b09153320	Fixed xilinx bram clock inverted config	2015-01-16 15:11:56 +01:00
Clifford Wolf	fd8c8d4fd3	Added FF cells to xilinx/cells_sim.v	2015-01-16 14:59:40 +01:00
Clifford Wolf	b197279f3c	Added Xilinx MUXF7 and MUXF8 support	2015-01-15 13:50:04 +01:00
Clifford Wolf	153d3dd4e0	Various cleanups in synth_xilinx command	2015-01-13 13:20:32 +01:00
Clifford Wolf	1d96277f5d	Added add_share_file Makefile macro	2015-01-08 00:23:18 +01:00
Clifford Wolf	38dfc5c580	added minimalistic xilinx sim models	2015-01-08 00:05:11 +01:00
Clifford Wolf	d1e38693d5	More Xilinx bram cleanups	2015-01-07 01:59:36 +01:00
Clifford Wolf	584c5f3937	Cleanups in xilinx bram descriptions	2015-01-07 01:28:18 +01:00