88 commits

Author	SHA1	Message	Date
David Shah	65716c9982	xilinx_dsp: Add multonly scratchpad var to bypass ... Signed-off-by: David Shah <dave@ds0.me>	2020-02-01 15:30:43 +00:00
Marcin Kościelnicki	666c6128a9	xilinx_dsp: Initial DSP48A/DSP48A1 support.	2019-12-22 20:51:14 +01:00
Eddie Hung	472b5d33a6	Merge pull request #1438 from YosysHQ/eddie/xilinx_dsp_comments ... Add notes and comments for xilinx_dsp	2019-10-08 10:53:30 -07:00
Eddie Hung	14e4aeece6	Fix comment	2019-10-04 22:31:04 -07:00
Eddie Hung	cf82b38478	Add comments for xilinx_dsp	2019-10-04 22:31:04 -07:00
Miodrag Milanovic	c0b14cfea7	Fixes for MSVC build	2019-10-04 16:29:46 +02:00
Eddie Hung	26657037b8	Update doc with max cascade chain of 20	2019-09-26 14:31:02 -07:00
Eddie Hung	5b9deef10d	Do not always zero out C (e.g. during cascade breaks)	2019-09-26 13:59:05 -07:00
Eddie Hung	95f0dd57df	Update doc	2019-09-26 13:44:41 -07:00
Eddie Hung	af59856ba1	xilinx_dsp_cascade to also cascade AREG and BREG	2019-09-26 13:29:18 -07:00
Eddie Hung	c0bb1d22e8	Remove newline	2019-09-26 10:31:55 -07:00
Eddie Hung	5f8917c984	Fix memory issue since SigSpec& could be invalidated	2019-09-25 16:45:51 -07:00
Eddie Hung	e556d48d45	Set [AB]CASCREG to legal values	2019-09-23 16:00:11 -07:00
Eddie Hung	b824a56cde	Comment to explain separating CREG packing	2019-09-23 13:58:10 -07:00
Eddie Hung	15dfbc8125	Separate out CREG packing into new pattern, to avoid conflict with PREG	2019-09-23 13:27:10 -07:00
Eddie Hung	53817b8575	Use new port/param overload in pmg	2019-09-20 14:21:22 -07:00
Eddie Hung	d122083a11	Output pattern matcher items as log_debug()	2019-09-20 12:42:28 -07:00
Eddie Hung	eb597431f0	Do not run xilinx_dsp_cascadeAB for now	2019-09-20 12:18:37 -07:00
Eddie Hung	b0ad2592be	Run until convergence	2019-09-20 12:04:16 -07:00
Eddie Hung	ed187ef1cf	Add a xilinx_dsp_cascade matcher for PCIN -> PCOUT	2019-09-20 10:00:09 -07:00
Eddie Hung	1b88211ec6	Clarify	2019-09-19 21:58:34 -07:00
Eddie Hung	c83a667555	Fix width of D	2019-09-19 18:08:46 -07:00
Eddie Hung	a8bc460805	Use ID() macro	2019-09-19 16:13:22 -07:00
Eddie Hung	37b0fc17e3	Re-enable sign extension for C input	2019-09-19 15:40:17 -07:00
Eddie Hung	44bf4ac35c	Add doc on pattern detector for overflow	2019-09-18 12:35:24 -07:00
Eddie Hung	347cbf59bd	Check overflow condition is power of 2 without using int32	2019-09-18 12:16:03 -07:00
Eddie Hung	1f18736d20	Add support for overflow using pattern detector	2019-09-18 09:39:59 -07:00
Eddie Hung	3a39073302	Set more ports explicitly	2019-09-12 17:10:43 -07:00
Eddie Hung	f3081c20e7	Add support for A1 and B1 registers	2019-09-11 17:16:46 -07:00
Eddie Hung	6fa6bf483c	Rename {A,B} -> {A2,B2}	2019-09-11 16:21:24 -07:00
Eddie Hung	690b1a064d	Add PCOUT -> PCIN non-shifted cascading	2019-09-11 13:48:45 -07:00
Eddie Hung	d232e6a6cd	Input registers to add DSP as new siguser to block upstream packing	2019-09-11 11:46:21 -07:00
Eddie Hung	e5bdb521fa	More cleanup	2019-09-11 10:55:45 -07:00
Eddie Hung	0d709d2bb5	Add support for A/B/C/D/AD reset	2019-09-11 10:15:19 -07:00
Eddie Hung	ded805ae5d	Add support for RSTM	2019-09-11 07:34:14 -07:00
Eddie Hung	b08797da6b	Only pack out registers if \init is zero or x; then remove \init from PREG	2019-09-10 21:33:14 -07:00
Eddie Hung	37a34eeb04	Fix RSTP	2019-09-10 20:56:13 -07:00
Eddie Hung	af147d1430	Add support for RSTP	2019-09-10 20:51:48 -07:00
Eddie Hung	c6df55a9e7	enpol -> cepol	2019-09-10 18:59:03 -07:00
Eddie Hung	e64e650f9c	Update help text	2019-09-10 16:35:10 -07:00
Eddie Hung	d30b2a6d7e	Update xilinx_dsp help text	2019-09-10 16:33:13 -07:00
Eddie Hung	cba63fe72b	Oops	2019-09-09 22:06:23 -07:00
Eddie Hung	02cf9933b9	Support subtraction as well	2019-09-09 21:39:42 -07:00
Eddie Hung	31e60353ac	Support TWO24	2019-09-09 21:11:41 -07:00
Eddie Hung	0bb6fd8448	Refactor	2019-09-09 20:58:54 -07:00
Eddie Hung	5a6552e56b	Add initial USE_SIMD=FOUR12 support	2019-09-09 20:57:20 -07:00
Eddie Hung	74a5c802f7	Pack CREG	2019-09-06 21:01:36 -07:00
Eddie Hung	5344bfe637	Perform D replacement properly	2019-09-06 15:46:15 -07:00
Eddie Hung	74eac76699	Add support for DREG	2019-09-06 15:32:26 -07:00
Eddie Hung	8246062acf	Fix enable polarity	2019-09-06 14:36:10 -07:00