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https://github.com/YosysHQ/yosys
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Add support for RSTP
This commit is contained in:
Eddie Hung
parent
c6df55a9e7
commit
af147d1430
passes/pmgen
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@ -273,7 +273,8 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
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log("postAdd: %s\n", log_id(st.postAdd, "--"));
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log("postAddMux: %s\n", log_id(st.postAddMux, "--"));
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log("ffP: %s\n", log_id(st.ffP, "--"));
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log("ffPmux: %s\n", log_id(st.ffPmux, "--"));
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log("ffPcemux: %s\n", log_id(st.ffPcemux, "--"));
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log("ffPrstmux: %s\n", log_id(st.ffPrstmux, "--"));
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#endif
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log("Analysing %s.%s for Xilinx DSP packing.\n", log_id(pm.module), log_id(st.dsp));
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@ -431,10 +432,17 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
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pm.autoremove(st.ffM);
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}
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if (st.ffP) {
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if (st.ffPmux) {
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SigSpec S = st.ffPmux->getPort("\\S");
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if (st.ffPrstmux) {
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SigSpec S = st.ffPrstmux->getPort("\\S");
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cell->setPort("\\RSTP", st.ffPrstpol ? S : pm.module->Not(NEW_ID, S));
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st.ffPrstmux->connections_.at("\\Y").replace(P, pm.module->addWire(NEW_ID, GetSize(P)));
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}
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else
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cell->setPort("\\RSTP", State::S1);
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if (st.ffPcemux) {
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SigSpec S = st.ffPcemux->getPort("\\S");
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cell->setPort("\\CEP", st.ffPcepol ? S : pm.module->Not(NEW_ID, S));
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st.ffPmux->connections_.at("\\Y").replace(P, pm.module->addWire(NEW_ID, GetSize(P)));
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st.ffPcemux->connections_.at("\\Y").replace(P, pm.module->addWire(NEW_ID, GetSize(P)));
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}
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else
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cell->setPort("\\CEP", State::S1);
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@ -4,19 +4,18 @@ state <std::function<SigSpec(const SigSpec&)>> unextend
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state <SigBit> clock
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state <SigSpec> sigA sigffAmuxY sigB sigffBmuxY sigC sigffCmuxY sigD sigffDmuxY sigM sigP
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state <IdString> postAddAB postAddMuxAB
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state <bool> ffAcepol ffADcepol ffBcepol ffCcepol ffDcepol ffMcepol ffPcepol
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state <bool> ffAcepol ffADcepol ffBcepol ffCcepol ffDcepol ffMcepol ffPcepol ffPrstpol
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state <int> ffPoffset
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state <Cell*> ffAD ffADmux ffA ffAmux ffB ffBmux ffC ffCmux ffD ffDmux ffM ffMmux ffP ffPmux
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state <Cell*> ffAD ffADmux ffA ffAmux ffB ffBmux ffC ffCmux ffD ffDmux ffM ffMmux ffP ffPcemux ffPrstmux
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// subpattern
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state <SigSpec> argQ argD
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state <bool> ffcepol
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state <Cell*> ffmux
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state <bool> ffcepol ffrstpol
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udata <SigSpec> dffD dffQ
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udata <SigBit> dffclock
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udata <Cell*> dff dffcemux
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udata <bool> dffcepol
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udata <Cell*> dff dffcemux dffrstmux
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udata <bool> dffcepol dffrstpol
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match dsp
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select dsp->type.in(\DSP48E1)
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@ -213,11 +212,11 @@ code sigC sigP
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}
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endcode
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code argD ffP ffPmux ffPcepol sigP clock
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code argD ffP ffPcemux ffPrstmux ffPcepol ffPrstpol sigP clock
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if (param(dsp, \PREG).as_int() == 0) {
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// If ffMmux and no postAdd new-value net must have exactly three users: ffMmux, ffM and ffPmux
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// If ffMmux and no postAdd new-value net must have exactly three users: ffMmux, ffM and ffPcemux
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if ((ffMmux && !postAdd && nusers(sigP) == 3) ||
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// Otherwise new-value net must have exactly two users: dsp and ffPmux
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// Otherwise new-value net must have exactly two users: dsp and ffPcemux
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((!ffMmux || postAdd) && nusers(sigP) == 2)) {
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argD = sigP;
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subpattern(out_dffe);
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@ -225,8 +224,10 @@ code argD ffP ffPmux ffPcepol sigP clock
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ffP = dff;
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clock = dffclock;
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if (dffcemux) {
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ffPmux = dffcemux;
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ffPcemux = dffcemux;
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ffPcepol = dffcepol;
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ffPrstmux = dffrstmux;
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ffPrstpol = dffrstpol;
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}
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sigP = dffQ;
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}
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@ -343,8 +344,8 @@ endcode
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// #######################
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subpattern out_dffe
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arg argD clock ffcepol
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arg unextend ffmux
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arg argD argQ clock
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arg unextend
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match ffcemux
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select ffcemux->type.in($mux)
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@ -356,14 +357,11 @@ match ffcemux
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// new-value net must have exactly two users: (upstream) and ffcemux
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select nusers(port(ffcemux, BA)) == 2
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slice offset GetSize(port(ffcemux, \Y))
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filter offset+GetSize(argD) <= GetSize(port(ffcemux, \Y))
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filter port(ffcemux, BA).extract(offset, GetSize(argD)) == argD
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define <IdString> AB (BA == \B ? \A : \B)
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// keep-last-value net must have at least three users: ffcemux, ff, downstream sink(s)
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select nusers(port(ffcemux, AB)) >= 3
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slice offset GetSize(port(ffcemux, \Y))
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filter GetSize(unextend(port(ffcemux, BA))) <= GetSize(argD)
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filter unextend(port(ffcemux, BA)) == argD.extract(0, GetSize(unextend(port(ffcemux, BA))))
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// Remaining bits on argD must not have any other users
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@ -374,24 +372,62 @@ match ffcemux
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semioptional
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endmatch
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code argD ffmux
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code argD argQ
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if (ffcemux) {
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dffcemux = ffcemux;
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dffcepol = ffcepol;
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argD = port(ffcemux, \Y);
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ffmux = ffcemux;
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argQ = port(ffcemux, ffcepol ? \A : \B);
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}
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else
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dffcemux = nullptr;
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endcode
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match ffrstmux
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if !argQ.empty()
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select ffrstmux->type.in($mux)
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// ffrstmux output must have two users: ffrstmux and ff.D
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select nusers(port(ffrstmux, \Y)) == 2
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filter GetSize(port(ffrstmux, \Y)) >= GetSize(argD)
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choice <IdString> BA {\B, \A}
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// DSP48E1 only supports reset to zero
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select port(ffrstmux, BA).is_fully_zero()
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define <IdString> AB (BA == \B ? \A : \B)
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// keep-last-value net must have exactly 2 users: ffrstmux, ffcemux/<upstream>
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select nusers(port(ffrstmux, AB)) == 2
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slice offset GetSize(port(ffrstmux, \Y))
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filter GetSize(port(ffrstmux, AB)) <= GetSize(argD)
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filter port(ffrstmux, AB) == argD.extract(0, GetSize(port(ffrstmux, AB)))
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// Remaining bits on argD must not have any other users
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filter nusers(argD.extract_end(GetSize(port(ffrstmux, AB)))) <= 1
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define <bool> pol (AB == \A)
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set ffrstpol pol
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semioptional
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endmatch
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code argD argQ
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if (ffrstmux) {
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dffrstmux = ffrstmux;
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dffrstpol = ffrstpol;
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argD = port(ffrstmux, \Y);
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}
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else {
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dffrstmux = nullptr;
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argQ = SigSpec();
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}
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endcode
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match ff_enable
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if ffmux
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if !argQ.empty()
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select ff_enable->type.in($dff)
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// DSP48E1 does not support clock inversion
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select param(ff_enable, \CLK_POLARITY).as_bool()
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index <SigSpec> port(ff_enable, \D) === argD
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index <SigSpec> port(ff_enable, \Q) === port(ffmux, ffcepol ? \A : \B)
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index <SigSpec> port(ff_enable, \Q) === argQ
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endmatch
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match ff
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@ -421,7 +457,7 @@ code
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}
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dffclock = port(dff, \CLK);
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}
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// No enable mux possible without flop
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else if (ffmux)
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// No enable/reset mux possible without flop
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else if (ffcemux || ffrstmux)
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reject;
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endcode
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