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https://github.com/YosysHQ/yosys
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enpol -> cepol
This commit is contained in:
Eddie Hung
parent
86700c2bea
commit
c6df55a9e7
2 changed files with 59 additions and 57 deletions
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@ -297,7 +297,7 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
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if (st.ffAD) {
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if (st.ffADmux) {
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SigSpec S = st.ffADmux->getPort("\\S");
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cell->setPort("\\CEAD", st.ffADenpol ? S : pm.module->Not(NEW_ID, S));
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cell->setPort("\\CEAD", st.ffADcepol ? S : pm.module->Not(NEW_ID, S));
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}
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else
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cell->setPort("\\CEAD", State::S1);
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@ -346,10 +346,10 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
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A.replace(Q, D);
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if (st.ffAmux) {
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SigSpec Y = st.ffAmux->getPort("\\Y");
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SigSpec AB = st.ffAmux->getPort(st.ffAenpol ? "\\B" : "\\A");
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SigSpec AB = st.ffAmux->getPort(st.ffAcepol ? "\\B" : "\\A");
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SigSpec S = st.ffAmux->getPort("\\S");
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A.replace(Y, AB);
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cell->setPort("\\CEA2", st.ffAenpol ? S : pm.module->Not(NEW_ID, S));
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cell->setPort("\\CEA2", st.ffAcepol ? S : pm.module->Not(NEW_ID, S));
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}
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else
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cell->setPort("\\CEA2", State::S1);
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@ -364,10 +364,10 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
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B.replace(Q, D);
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if (st.ffBmux) {
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SigSpec Y = st.ffBmux->getPort("\\Y");
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SigSpec AB = st.ffBmux->getPort(st.ffBenpol ? "\\B" : "\\A");
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SigSpec AB = st.ffBmux->getPort(st.ffBcepol ? "\\B" : "\\A");
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SigSpec S = st.ffBmux->getPort("\\S");
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B.replace(Y, AB);
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cell->setPort("\\CEB2", st.ffBenpol ? S : pm.module->Not(NEW_ID, S));
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cell->setPort("\\CEB2", st.ffBcepol ? S : pm.module->Not(NEW_ID, S));
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}
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else
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cell->setPort("\\CEB2", State::S1);
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@ -383,11 +383,11 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
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if (st.ffCmux) {
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SigSpec Y = st.ffCmux->getPort("\\Y");
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SigSpec AB = st.ffCmux->getPort(st.ffCenpol ? "\\B" : "\\A");
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SigSpec AB = st.ffCmux->getPort(st.ffCcepol ? "\\B" : "\\A");
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SigSpec S = st.ffCmux->getPort("\\S");
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C.replace(Y, AB);
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cell->setPort("\\CEC", st.ffCenpol ? S : pm.module->Not(NEW_ID, S));
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cell->setPort("\\CEC", st.ffCcepol ? S : pm.module->Not(NEW_ID, S));
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}
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else
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cell->setPort("\\CEC", State::S1);
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@ -403,11 +403,11 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
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if (st.ffDmux) {
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SigSpec Y = st.ffDmux->getPort("\\Y");
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SigSpec AB = st.ffDmux->getPort(st.ffDenpol ? "\\B" : "\\A");
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SigSpec AB = st.ffDmux->getPort(st.ffDcepol ? "\\B" : "\\A");
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SigSpec S = st.ffDmux->getPort("\\S");
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D_.replace(Y, AB);
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cell->setPort("\\CED", st.ffDenpol ? S : pm.module->Not(NEW_ID, S));
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cell->setPort("\\CED", st.ffDcepol ? S : pm.module->Not(NEW_ID, S));
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}
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else
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cell->setPort("\\CED", State::S1);
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@ -418,7 +418,7 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
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if (st.ffM) {
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if (st.ffMmux) {
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SigSpec S = st.ffMmux->getPort("\\S");
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cell->setPort("\\CEM", st.ffMenpol ? S : pm.module->Not(NEW_ID, S));
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cell->setPort("\\CEM", st.ffMcepol ? S : pm.module->Not(NEW_ID, S));
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pm.autoremove(st.ffMmux);
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}
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else
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@ -433,7 +433,7 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
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if (st.ffP) {
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if (st.ffPmux) {
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SigSpec S = st.ffPmux->getPort("\\S");
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cell->setPort("\\CEP", st.ffPenpol ? S : pm.module->Not(NEW_ID, S));
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cell->setPort("\\CEP", st.ffPcepol ? S : pm.module->Not(NEW_ID, S));
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st.ffPmux->connections_.at("\\Y").replace(P, pm.module->addWire(NEW_ID, GetSize(P)));
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}
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else
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@ -4,18 +4,19 @@ state <std::function<SigSpec(const SigSpec&)>> unextend
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state <SigBit> clock
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state <SigSpec> sigA sigffAmuxY sigB sigffBmuxY sigC sigffCmuxY sigD sigffDmuxY sigM sigP
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state <IdString> postAddAB postAddMuxAB
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state <bool> ffAenpol ffADenpol ffBenpol ffCenpol ffDenpol ffMenpol ffPenpol
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state <bool> ffAcepol ffADcepol ffBcepol ffCcepol ffDcepol ffMcepol ffPcepol
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state <int> ffPoffset
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state <Cell*> ffAD ffADmux ffA ffAmux ffB ffBmux ffC ffCmux ffD ffDmux ffM ffMmux ffP ffPmux
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// subpattern
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state <SigSpec> argQ argD
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state <bool> ffenpol
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state <bool> ffcepol
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state <Cell*> ffmux
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udata <SigSpec> dffD dffQ
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udata <SigBit> dffclock
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udata <Cell*> dff dffcemux
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udata <bool> dffenpol
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udata <bool> dffcepol
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match dsp
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select dsp->type.in(\DSP48E1)
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@ -53,7 +54,7 @@ code unextend sigA sigB sigC sigD sigM
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sigM = P;
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endcode
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code argQ ffAD ffADmux ffADenpol sigA clock
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code argQ ffAD ffADmux ffADcepol sigA clock
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if (param(dsp, \ADREG).as_int() == 0) {
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argQ = sigA;
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subpattern(in_dffe);
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@ -62,7 +63,7 @@ code argQ ffAD ffADmux ffADenpol sigA clock
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clock = dffclock;
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if (dffcemux) {
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ffADmux = dffcemux;
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ffADenpol = dffenpol;
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ffADcepol = dffcepol;
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}
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sigA = dffD;
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}
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@ -99,7 +100,7 @@ code sigA sigD
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}
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endcode
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code argQ ffA ffAmux ffAenpol sigA clock ffAD ffADmux ffADenpol
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code argQ ffA ffAmux ffAcepol sigA clock ffAD ffADmux ffADcepol
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// Only search for ffA if there was a pre-adder
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// (otherwise ffA would have been matched as ffAD)
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if (preAdd) {
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@ -111,7 +112,7 @@ code argQ ffA ffAmux ffAenpol sigA clock ffAD ffADmux ffADenpol
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clock = dffclock;
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if (dffcemux) {
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ffAmux = dffcemux;
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ffAenpol = dffenpol;
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ffAcepol = dffcepol;
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}
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sigA = dffD;
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}
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@ -123,11 +124,11 @@ code argQ ffA ffAmux ffAenpol sigA clock ffAD ffADmux ffADenpol
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log_assert(!ffA && !ffAmux);
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std::swap(ffA, ffAD);
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std::swap(ffAmux, ffADmux);
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ffAenpol = ffADenpol;
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ffAcepol = ffADcepol;
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}
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endcode
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code argQ ffB ffBmux ffBenpol sigB clock
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code argQ ffB ffBmux ffBcepol sigB clock
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if (param(dsp, \BREG).as_int() == 0) {
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argQ = sigB;
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subpattern(in_dffe);
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@ -136,14 +137,14 @@ code argQ ffB ffBmux ffBenpol sigB clock
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clock = dffclock;
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if (dffcemux) {
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ffBmux = dffcemux;
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ffBenpol = dffenpol;
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ffBcepol = dffcepol;
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}
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sigB = dffD;
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}
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}
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endcode
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code argQ ffD ffDmux ffDenpol sigD clock
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code argQ ffD ffDmux ffDcepol sigD clock
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if (param(dsp, \DREG).as_int() == 0) {
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argQ = sigD;
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subpattern(in_dffe);
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@ -152,14 +153,14 @@ code argQ ffD ffDmux ffDenpol sigD clock
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clock = dffclock;
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if (dffcemux) {
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ffDmux = dffcemux;
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ffDenpol = dffenpol;
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ffDcepol = dffcepol;
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}
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sigD = dffD;
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}
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}
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endcode
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code argD ffM ffMmux ffMenpol sigM sigP clock
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code argD ffM ffMmux ffMcepol sigM sigP clock
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if (param(dsp, \MREG).as_int() == 0 && nusers(sigM) == 2) {
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argD = sigM;
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subpattern(out_dffe);
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@ -168,7 +169,7 @@ code argD ffM ffMmux ffMenpol sigM sigP clock
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clock = dffclock;
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if (dffcemux) {
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ffMmux = dffcemux;
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ffMenpol = dffenpol;
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ffMcepol = dffcepol;
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}
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sigM = dffQ;
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}
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@ -212,7 +213,7 @@ code sigC sigP
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}
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endcode
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code argD ffP ffPmux ffPenpol sigP clock
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code argD ffP ffPmux ffPcepol sigP clock
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if (param(dsp, \PREG).as_int() == 0) {
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// If ffMmux and no postAdd new-value net must have exactly three users: ffMmux, ffM and ffPmux
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if ((ffMmux && !postAdd && nusers(sigP) == 3) ||
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@ -225,7 +226,7 @@ code argD ffP ffPmux ffPenpol sigP clock
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clock = dffclock;
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if (dffcemux) {
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ffPmux = dffcemux;
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ffPenpol = dffenpol;
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ffPcepol = dffcepol;
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}
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sigP = dffQ;
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}
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@ -250,7 +251,7 @@ code sigC
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sigC = port(postAddMux, postAddMuxAB == \A ? \B : \A);
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endcode
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code argQ ffC ffCmux ffCenpol sigC clock
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code argQ ffC ffCmux ffCcepol sigC clock
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if (param(dsp, \CREG).as_int() == 0) {
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argQ = sigC;
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subpattern(in_dffe);
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@ -259,7 +260,7 @@ code argQ ffC ffCmux ffCenpol sigC clock
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clock = dffclock;
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if (dffcemux) {
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ffCmux = dffcemux;
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ffCenpol = dffenpol;
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ffCcepol = dffcepol;
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}
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sigC = dffD;
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}
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@ -273,7 +274,7 @@ endcode
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// #######################
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subpattern in_dffe
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arg argQ clock ffenpol
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arg argQ clock ffcepol
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match ff
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select ff->type.in($dff)
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@ -325,15 +326,15 @@ match ffcemux
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filter offset+GetSize(argQ) <= GetSize(port(ffcemux, \Y))
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filter port(ffcemux, AB).extract(offset, GetSize(argQ)) == argQ
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define <bool> pol (AB == \A)
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set ffenpol pol
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set ffcepol pol
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semioptional
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endmatch
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code
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if (ffcemux) {
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dffcemux = ffcemux;
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dffenpol = ffenpol;
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dffD = port(ffcemux, dffenpol ? \B : \A);
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dffcepol = ffcepol;
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dffD = port(ffcemux, dffcepol ? \B : \A);
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}
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else
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dffcemux = nullptr;
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@ -342,42 +343,43 @@ endcode
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// #######################
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subpattern out_dffe
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arg argD clock ffenpol
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arg unextend
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arg argD clock ffcepol
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arg unextend ffmux
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match ffmux
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select ffmux->type.in($mux)
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// ffmux output must have two users: ffmux and ff.D
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select nusers(port(ffmux, \Y)) == 2
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filter GetSize(port(ffmux, \Y)) >= GetSize(argD)
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match ffcemux
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select ffcemux->type.in($mux)
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// ffcemux output must have two users: ffcemux and ff.D
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select nusers(port(ffcemux, \Y)) == 2
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filter GetSize(port(ffcemux, \Y)) >= GetSize(argD)
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choice <IdString> BA {\B, \A}
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// new-value net must have exactly two users: (upstream) and ffmux
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select nusers(port(ffmux, BA)) == 2
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// new-value net must have exactly two users: (upstream) and ffcemux
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select nusers(port(ffcemux, BA)) == 2
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slice offset GetSize(port(ffmux, \Y))
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filter offset+GetSize(argD) <= GetSize(port(ffmux, \Y))
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filter port(ffmux, BA).extract(offset, GetSize(argD)) == argD
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slice offset GetSize(port(ffcemux, \Y))
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filter offset+GetSize(argD) <= GetSize(port(ffcemux, \Y))
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filter port(ffcemux, BA).extract(offset, GetSize(argD)) == argD
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define <IdString> AB (BA == \B ? \A : \B)
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// keep-last-value net must have at least three users: ffmux, ff, downstream sink(s)
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select nusers(port(ffmux, AB)) >= 3
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// keep-last-value net must have at least three users: ffcemux, ff, downstream sink(s)
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select nusers(port(ffcemux, AB)) >= 3
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filter GetSize(unextend(port(ffmux, BA))) <= GetSize(argD)
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filter unextend(port(ffmux, BA)) == argD.extract(0, GetSize(unextend(port(ffmux, BA))))
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filter GetSize(unextend(port(ffcemux, BA))) <= GetSize(argD)
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filter unextend(port(ffcemux, BA)) == argD.extract(0, GetSize(unextend(port(ffcemux, BA))))
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// Remaining bits on argD must not have any other users
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filter nusers(argD.extract_end(GetSize(unextend(port(ffmux, BA))))) <= 1
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filter nusers(argD.extract_end(GetSize(unextend(port(ffcemux, BA))))) <= 1
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define <bool> pol (AB == \A)
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set ffenpol pol
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set ffcepol pol
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semioptional
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endmatch
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code argD
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if (ffmux) {
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dffcemux = ffmux;
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dffenpol = ffenpol;
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argD = port(ffmux, \Y);
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code argD ffmux
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if (ffcemux) {
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dffcemux = ffcemux;
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dffcepol = ffcepol;
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argD = port(ffcemux, \Y);
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ffmux = ffcemux;
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}
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else
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dffcemux = nullptr;
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@ -389,7 +391,7 @@ match ff_enable
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// DSP48E1 does not support clock inversion
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select param(ff_enable, \CLK_POLARITY).as_bool()
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index <SigSpec> port(ff_enable, \D) === argD
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index <SigSpec> port(ff_enable, \Q) === port(ffmux, ffenpol ? \A : \B)
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index <SigSpec> port(ff_enable, \Q) === port(ffmux, ffcepol ? \A : \B)
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endmatch
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match ff
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