github-actions[bot]
e57a2b9442
Bump version
2025-07-11 00:25:36 +00:00
Emil J
dfe86b50d8
Merge pull request #5217 from rocallahan/fix-importSigSpecWorker-leak
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Fix space leak in `SatGen::importSigSpecWorker()` by avoiding `log_id…
2025-07-10 19:56:56 +02:00
Emil J
14aad097f0
Merge pull request #5190 from YosysHQ/emil/dfflibmap-fix-negated-next_state
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dfflibmap: propagate negated next_state to output correctly
2025-07-10 19:50:02 +02:00
Emil J. Tywoniak
7fe817c52f
dfflibmap: test negated state next_state with mixed polarities
2025-07-10 18:54:43 +02:00
N. Engelhardt
02323295b0
Merge pull request #5179 from YosysHQ/krys/assert2cover
2025-07-10 14:53:22 +02:00
N. Engelhardt
d21a553fdc
Merge pull request #5218 from YosysHQ/nak/limit_ub
2025-07-10 14:53:11 +02:00
Emil J. Tywoniak
f34c4f2e26
log: deduplicate unescape_id from log_id
2025-07-09 16:20:27 +02:00
N. Engelhardt
e47f5369fd
verificsva: check -L value is small enough for code to work
2025-07-09 15:58:35 +02:00
Emil J
9334a5c275
Merge pull request #5216 from YosysHQ/emil/publish-libparse-header
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Install libparse.h for use in plugins
2025-07-09 14:28:59 +02:00
github-actions[bot]
7566af4a4b
Bump version
2025-07-09 00:25:57 +00:00
Robert O'Callahan
743df9f0f9
Fix space leak in SatGen::importSigSpecWorker() by avoiding log_id().
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Calling `log_id()` leaks a copy of the ID into `log_id_cache` until the
end of the pass, which causes exorbitant memory usage.
See issue #5210 .
2025-07-08 23:53:38 +00:00
George Rennie
478b6a2b3f
kernel: treat zero width constant as zero
2025-07-08 19:37:59 +01:00
Emil J. Tywoniak
ad80e2bd39
libparse: install headers for use in plugins
2025-07-08 13:39:03 +02:00
Emil J
66035f706e
Merge pull request #5177 from YosysHQ/emil/rename-unescape
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rename: add -unescape
2025-07-08 10:45:11 +02:00
github-actions[bot]
e60cf3e2fa
Bump version
2025-07-08 00:25:06 +00:00
KrystalDelusion
1a215719e5
Merge pull request #5192 from garytwong/multiline-string
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verilog: support newline and hex escapes in string literals
2025-07-08 10:27:01 +12:00
Emil J. Tywoniak
658c7dd424
rename: fix help
2025-07-07 16:16:57 +02:00
Miodrag Milanovic
8af60b7e17
Next dev cycle
2025-07-07 12:40:53 +02:00
Miodrag Milanovic
60f126cd00
Release version 0.55
2025-07-07 11:26:04 +02:00
Emil J
468cbb800c
Merge pull request #5206 from yrabbit/cell-creation-script-5a
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Gowin. BUGFIX. Fix multi-line descriptions.
2025-07-07 10:36:42 +02:00
N. Engelhardt
642756a9c6
Merge pull request #5178 from jix/sva_cover_only_followed_by
2025-07-07 10:07:06 +02:00
github-actions[bot]
99f7d79abb
Bump version
2025-07-05 00:23:55 +00:00
Miodrag Milanović
afd0ba0099
Merge pull request #5208 from YosysHQ/micko/replace_const_exprs
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verific: enable replacing const exprs in static elaboration by default
2025-07-04 10:35:03 +02:00
Gary Wong
5feb1a1752
verilog: add support for SystemVerilog string literals.
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Differences are new escape sequences (including escaped newline
continuations and hex escapes) and triple-quoted literals.
2025-07-03 20:51:12 -06:00
Miodrag Milanovic
eed3bc243f
verific: enable replacing const exprs in static elaboration by default
2025-07-02 11:54:19 +02:00
YRabbit
85e7c68fc6
Gowin. BUGFIX. Fix multi-line descriptions.
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If let's say the enumeration of inputs took several lines, then all
after the first one were ignored. Since the first line ended with a
comma, an error was generated when trying to use the resulting file.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2025-07-02 12:39:18 +10:00
N. Engelhardt
7b0c1fe491
Merge pull request #5102 from YosysHQ/krys/verilog_no_select
2025-06-30 13:35:17 +00:00
Miodrag Milanović
54013c6da7
Merge pull request #5162 from YosysHQ/micko/attrmap
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Make attrmap able to alter memory attributes as well
2025-06-30 15:24:04 +02:00
github-actions[bot]
67583fee48
Bump version
2025-06-30 00:27:10 +00:00
KrystalDelusion
74575691a0
Merge pull request #5180 from YosysHQ/krys/test_asan
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Add ASAN to CI
2025-06-30 10:40:34 +12:00
Krystine Sherwin
017524d7a2
tests/verific: Don't ASAN verific
2025-06-28 11:33:18 +12:00
Krystine Sherwin
e6961d8c9f
CI: Test with ASAN as well
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New matrix variable for sanitizer, running `undefined` and `address` separately
(because they are mutually exclusive). Probably don't need to run both
sanitizers on both os targets, but it's probably fine.
2025-06-28 11:33:18 +12:00
Emil J. Tywoniak
2b659626a3
rename: add -unescape
2025-06-24 12:33:33 +02:00
Emil J
513f0f16dd
Merge pull request #5173 from RonxBulld/refine_setup_shutdown_flags
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Allows calling yosys_shutdown and then yosys_setup to restart.
2025-06-24 12:32:52 +02:00
Emil J. Tywoniak
73cbcffbbb
fixup! dfflibmap: propagate negated next_state to output correctly
2025-06-24 12:31:30 +02:00
Emil J. Tywoniak
778079b058
dfflibmap: propagate negated next_state to output correctly
2025-06-24 12:01:12 +02:00
github-actions[bot]
a0a77cd1d0
Bump version
2025-06-24 00:24:55 +00:00
Gary Wong
34a2abeddb
verilog: fix parser "if" memory errors.
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Fix buggy memory allocation introduced in #5152 :
1) clean up ast_stack to reflect AST node rearrangement when necessary,
to avoid dangling pointer;
2) call free_attr() on unused attribute list when no new syntax node is
created, to avoid leaking it.
2025-06-22 23:57:42 -04:00
George Rennie
170933ecb0
Merge pull request #5165 from georgerennie/george/opt_dff_uaf
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opt_dff: don't remove cells until all have been visited to prevent UAF
2025-06-20 23:33:26 +01:00
Krystine Sherwin
beaca05b40
Include boxes in attrmap
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Rename `selected_members` iterator to memb.
Add comment on `selected_processes` loop for clarity.
2025-06-21 09:49:56 +12:00
github-actions[bot]
44aa313ba9
Bump version
2025-06-20 00:24:40 +00:00
garytwong
834a7294b7
verilog: fix string literal regular expression ( #5187 )
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* verilog: fix string literal regular expression.
A backslash was improperly quoted, causing string literal matching
to fail when the final token before a closing quote was an escaped
backslash.
* verilog: add regression test for string literal regex bug.
Test for bug triggered by escaped backslash immediately before
closing quote (introduced in ca7d94af40aa7eaf
2025-06-19 12:41:18 -04:00
github-actions[bot]
cd71f190cd
Bump version
2025-06-14 00:24:06 +00:00
Krystine Sherwin
fa68299b25
tests/verific: Add chformal tests
2025-06-14 11:06:38 +12:00
Krystine Sherwin
45131f4425
chformal: Add -assert2cover option
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Also add to chformal tests.
2025-06-14 10:54:23 +12:00
KrystalDelusion
efa30dfdf8
Merge pull request #5176 from YosysHQ/krys/no_cxxopt_split
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driver.cc: Don't split options on commas
2025-06-14 10:39:28 +12:00
Jannis Harder
f019e44e74
verificsva: Support the followed-by operator in cover mode
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The implementation for the implication operator in cover mode actually
implements the followed-by operator, so we can re-use it unchanged.
It is not always the correct behavior for the implication operator in
cover mode, but a) it will only cause false positives not miss anything
so if the behavior is unexpected it will be visible in the produced
traces, b) it is unlikely to make a difference for most properties one
would practically use in cover mode, c) at least one other widely used
SVA implementations behaves the same way and d) it's not clear whether
we can fix this without rewriting most of verificsva.cc
2025-06-13 21:27:31 +02:00
KrystalDelusion
4ade617c41
driver.cc: Don't split options on commas
2025-06-13 10:31:53 +12:00
KrystalDelusion
67f8de54dc
Merge pull request #5160 from garytwong/fast-lex
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verilog: improve string literal matching speed (fixes #5076 )
2025-06-13 09:57:01 +12:00
KrystalDelusion
82888580ac
Merge pull request #5152 from garytwong/unique-if
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verilog: implement SystemVerilog unique/unique0/priority if semantics.
2025-06-13 09:56:53 +12:00
