N. Engelhardt
d5b38af4a7
Merge pull request #5550 from YosysHQ/nak/dont_merge_properties
2025-12-22 16:54:43 +01:00
Robert O'Callahan
46cb05c471
Pass IdString by value instead of by const reference.
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When IdString refcounting was expensive, it made sense to pass it by const reference
instead of by value, to avoid refcount churn. Now that IdString is not refcounted,
it's slightly more efficient to pass it by value.
2025-12-22 01:52:59 +00:00
N. Engelhardt
45d654e2d7
avoid merging formal properties
2025-12-17 20:25:24 +01:00
KrystalDelusion
529886f7fb
Merge pull request #5473 from YosysHQ/krys/unsized_params
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Handle unsized params
2025-11-12 07:14:44 +13:00
Emil J. Tywoniak
8f53d21ea7
simplify: refactor specific package import
2025-11-10 14:26:10 +01:00
Rahul Bhagwat
224109151d
add specific package imports and tests
2025-11-08 23:05:10 +05:30
Krystine Sherwin
7302bf9a66
Add CONST_FLAG_UNSIZED
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In order to support unsized constants being used as parameters, the `const` struct needs to know if it is unsized (so that the parameter can be used to set the size).
Add unsized flag to param value serialization and rtlil back-/front-end.
Add cell params to `tests/rtlil/everything.v`.
2025-11-07 17:45:07 +13:00
Krystine Sherwin
a5cc905184
simplify.cc: Fix unsized const in params
2025-11-07 15:52:24 +13:00
Emil J. Tywoniak
5cfe6a9c1e
reduce OS ifdefs, refactor getting dirs and filenames from paths to files
2025-10-14 15:46:17 +02:00
Jannis Harder
79e05a195d
verilog: Bufnorm cell backend and frontend support
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This makes the Verilog backend handle the $connect and $input_port
cells. This represents the undirected $connect cell using the `tran`
primitive, so we also extend the frontend to support this.
2025-09-17 14:01:09 +02:00
Robert O'Callahan
a1141f1a4c
Remove some unnecessary .c_str() calls to the result of unescape_id()
2025-09-16 23:12:14 +00:00
Robert O'Callahan
d276529d46
Remove .c_str() calls from parameters to log_file_info()
2025-09-16 23:06:28 +00:00
Robert O'Callahan
548deba259
Remove .c_str() calls from parameters to log_file_warning()
2025-09-16 23:03:45 +00:00
Robert O'Callahan
a7c46f7b4a
Remove .c_str() calls from parameters to log_warning()/log_warning_noprefix()
2025-09-16 23:02:16 +00:00
Robert O'Callahan
d1fd6de6da
Remove .c_str() calls from parameters to log_header()
2025-09-16 23:00:42 +00:00
Robert O'Callahan
5ac6858f26
Remove .c_str() from log_cmd_error() and log_file_error() parameters
2025-09-16 22:59:08 +00:00
Robert O'Callahan
f65ca488ec
Update frontends to avoid bits()
2025-09-16 03:17:23 +00:00
Jannis Harder
193b057983
Merge pull request #5341 from rocallahan/more-varargs-conversion
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More varargs conversion
2025-09-12 18:09:42 +02:00
Robert O'Callahan
733b6f0124
Remove unnecessary usage of .c_str() in parameters to input_error()
2025-09-12 06:03:05 +00:00
Robert O'Callahan
ad4ef8b775
Make AstNode::input_error use C++ stringf machinery
2025-09-12 06:01:32 +00:00
Robert O'Callahan
e0ae7b7af4
Remove .c_str() calls from log()/log_error()
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There are some leftovers, but this is an easy regex-based approach that removes most of them.
2025-09-11 20:59:37 +00:00
Robert O'Callahan
c7df6954b9
Remove .c_str() from stringf parameters
2025-09-01 23:34:42 +00:00
Emil J. Tywoniak
8582136a45
simplify: fix $initstate segfault
2025-08-12 12:39:36 +02:00
Emil J. Tywoniak
99ab73424d
verilog_location: rename location to Location to avoid conflict with Pass::location
2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
5195f81257
ast: fix import node
2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
740ed3fc1c
ast: refactor
2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
646c45e6b8
ast: remove null_check as dead code
2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
25d2a8ce3a
simplify: simplify
2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
97bc0088d8
simplify: std::gcd
2025-08-11 13:34:10 +02:00
Krystine Sherwin
d3e33a3be5
simplify.cc: Drop unused debug prints
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At least the ones added by this PR. There are some unused debug prints that are *changed* by this PR, but I've left them.
2025-08-11 13:34:10 +02:00
Krystine Sherwin
9b882c32c1
frontends/ast: More usage of auto
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For consistency.
2025-08-11 13:34:10 +02:00
Krystine Sherwin
0f7080ebf8
dpicall.cc: Fix sans-plugin function call
2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
ecec9a760b
ast, read_verilog: unify location types, reduce filename copying
2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
8bf750ecbb
neater errors, lost in the sauce of source
2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
b3bf588966
ast, read_verilog: refactoring
2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
84f0c5da73
ast: fix new memory safety bugs from rebase
2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
c8e0ac0c61
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-08-11 13:34:10 +02:00
Rahul Bhagwat
f12055d3e0
rm debug logs
2025-08-06 15:39:36 -04:00
Rahul Bhagwat
7e0157ba2b
fix whitespace issues
2025-08-06 15:32:36 -04:00
Rahul Bhagwat
fe59b6d3db
add safety checks and better name matching
2025-08-04 20:57:43 -04:00
Rahul Bhagwat
761015b23e
add separate module test
2025-08-03 23:48:33 -04:00
Rahul Bhagwat
b776283d79
implement package import
2025-08-03 23:31:54 -04:00
KrystalDelusion
5b8b5292ee
Merge pull request #4959 from YosysHQ/krys/primitive_array_error
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simplify: Skip AST_PRIMITIVE in AST_CELLARRAY
2025-07-21 10:26:00 +12:00
Emil J
378add3723
Merge pull request #5163 from YosysHQ/emil/fix-single-bit-vector-leak
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simplify: fix single_bit_vector memory leak
2025-06-04 17:00:54 +02:00
George Rennie
0fcf5c080d
Merge pull request #5158 from georgerennie/george/task_inout
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read_verilog/astsimplify: copy inout ports in and out of functions/tasks
2025-06-04 14:23:08 +01:00
Emil J. Tywoniak
c37b7b3bf4
simplify: fix single_bit_vector memory leak
2025-06-04 10:32:03 +02:00
George Rennie
45e8ff476e
read_verilog: copy inout ports in and out of functions/tasks
2025-05-31 01:09:03 +01:00
Krystine Sherwin
32ce23458f
read_verilog: Mark struct as custom type
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Being a custom type means that it will be resolved *before* (e.g.) a wire can use it as a type.
2025-05-26 12:19:33 +12:00
Emil J
4b8d42d22c
Merge pull request #5095 from YosysHQ/emil/one-bit-width
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rtlil: enable single-bit vector wires
2025-05-23 15:55:45 +02:00
Emil J. Tywoniak
5e72464a15
rtlil: enable single-bit vector wires
2025-05-12 13:23:29 +02:00
