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Code Activity
13593 commits 94 branches 53 tags 44 MiB
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882 commits

Author SHA1 Message Date
Eddie Hung
79fb291dbe Cleanup, call pmux2shiftx even without -nosrl 2019-04-22 12:14:37 -07:00
Eddie Hung
4486a98fd5 Merge remote-tracking branch 'origin/xc7srl' into xc7mux 2019-04-22 11:45:49 -07:00
Eddie Hung
ec88129a5c Update help message 2019-04-22 11:38:23 -07:00
Eddie Hung
4883391b63 Merge remote-tracking branch 'origin/master' into xaig 2019-04-22 11:19:52 -07:00
Eddie Hung
0e76718720 Move 'shregmap -tech xilinx' into map_cells 2019-04-22 10:45:39 -07:00
Eddie Hung
e300b1922c Merge remote-tracking branch 'origin/master' into xc7srl 2019-04-22 10:36:27 -07:00
Clifford Wolf
cf1ba46fa0 Re-added clean after techmap in synth_xilinx 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-22 09:03:11 +02:00
Eddie Hung
d342b5b135 Tidy up, fix for -nosrl 2019-04-21 15:33:03 -07:00
Eddie Hung
726e2da8f2 Merge branch 'map_cells_before_map_luts' into xc7srl 2019-04-21 14:28:55 -07:00
Eddie Hung
a3371e118b Merge branch 'master' into map_cells_before_map_luts 2019-04-21 14:24:50 -07:00
Eddie Hung
ae95aba60a Add comments 2019-04-21 14:16:59 -07:00
Eddie Hung
d99422411f Use new pmux2shiftx from #944, remove my old attempt 2019-04-21 14:16:34 -07:00
Eddie Hung
caec7f9d2c Merge remote-tracking branch 'origin/master' into xaig 2019-04-20 12:23:49 -07:00
Eddie Hung
13ad19482f Merge remote-tracking branch 'origin' into xc7srl 2019-04-20 10:41:43 -07:00
Eddie Hung
6008bb7002 Revert "synth_* with -retime option now calls abc with -D 1 as well" 
This reverts commit 9a6da9a79a.
 2019-04-18 07:59:16 -07:00
Eddie Hung
0642baabbc Merge branch 'master' into eddie/fix_retime 2019-04-18 07:57:17 -07:00
Eddie Hung
cbb85e40e8 Add MUXCY and XORCY to cells_box.v 2019-04-16 14:53:28 -07:00
Eddie Hung
aece97024d Fix spacing 2019-04-16 13:16:20 -07:00
Eddie Hung
53b19ab1f5 Make cells.box whiteboxes not blackboxes 2019-04-16 12:43:14 -07:00
Eddie Hung
5189695362 read_verilog cells_box.v before techmap 2019-04-16 12:41:56 -07:00
Eddie Hung
d259e6dc14 synth_xilinx: before abc read +/xilinx/cells_box.v 2019-04-16 11:21:46 -07:00
Eddie Hung
3ac4977b70 Add +/xilinx/cells_box.v containing models for ABC boxes 2019-04-16 11:21:03 -07:00
Eddie Hung
8c6cf07acf Revert "Add abc_box_id attribute to MUXF7/F8 cells" 
This reverts commit 8fbbd9b129.
 2019-04-16 11:14:59 -07:00
Eddie Hung
8fbbd9b129 Add abc_box_id attribute to MUXF7/F8 cells 2019-04-15 22:25:09 -07:00
Eddie Hung
538592067e Merge branch 'xaig' into xc7mux 2019-04-15 22:04:20 -07:00
Eddie Hung
04e466d5e4 Add support for synth_xilinx -abc9 and ignore abc9 -dress opt 2019-04-12 12:28:37 -07:00
Keith Rothman
1f9235ede5 Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-04-12 09:35:15 -07:00
Eddie Hung
233edf00fe Fix cells_map.v some more 2019-04-11 10:48:14 -07:00
Eddie Hung
8658b56a08 More fine tuning 2019-04-11 10:08:05 -07:00
Eddie Hung
0ec8564099 Fix cells_map.v 2019-04-11 10:04:58 -07:00
Eddie Hung
bca3779657 Fix typo 2019-04-11 09:25:19 -07:00
Eddie Hung
87b8d29a90 Juggle opt calls in synth_xilinx 2019-04-11 09:13:39 -07:00
Eddie Hung
cd7b2de27f WIP for cells_map.v -- maybe working? 2019-04-10 18:05:09 -07:00
Eddie Hung
3d577586fd Try splitting $shiftx with Y_WIDTH > 1 into Y_WIDTH = 1 2019-04-10 16:15:23 -07:00
Eddie Hung
3f5dab0d09 Fix for when B_SIGNED = 1 2019-04-10 14:51:10 -07:00
Eddie Hung
32561332b2 Update doc for synth_xilinx 2019-04-10 14:48:58 -07:00
Eddie Hung
17a02df05c ff_map.v after abc 2019-04-10 12:36:06 -07:00
Eddie Hung
1ec949d5ed Tidy up 2019-04-10 09:02:42 -07:00
Eddie Hung
526aef9c2a Move map_cells to before map_luts 2019-04-10 08:50:31 -07:00
Eddie Hung
e0b46eb4cb WIP for $shiftx to wide mux 2019-04-10 08:49:55 -07:00
Eddie Hung
4dac9818bd Update LUT delays 2019-04-10 08:49:39 -07:00
Eddie Hung
9a6da9a79a synth_* with -retime option now calls abc with -D 1 as well 2019-04-10 08:32:53 -07:00
Eddie Hung
3e368593eb Add cells.lut to techlibs/xilinx/ 2019-04-09 14:33:37 -07:00
Eddie Hung
fd88ab5c83 synth_xilinx to call abc with -lut +/xilinx/cells.lut 2019-04-09 14:32:39 -07:00
Eddie Hung
b9e19071b8 Add delays to cells.box 2019-04-09 14:32:10 -07:00
Keith Rothman
e107ccdde8 Fix LUT6_2 definition. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-04-09 11:43:19 -07:00
Eddie Hung
f2042fc7c4 synth_xilinx with abc9 to use -box 2019-04-09 11:01:46 -07:00
Eddie Hung
2ae26b986c Add techlibs/xilinx/cells.box 2019-04-09 10:58:58 -07:00
Eddie Hung
3fc474aa73 Add support for synth_xilinx -abc9 and ignore abc9 -dress opt 2019-04-09 10:06:44 -07:00
Keith Rothman
5e0339855f Add additional cells sim models for core 7-series primatives. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-04-09 09:01:53 -07:00