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yosys/techlibs/xilinx
2019-04-15 22:25:09 -07:00
..
tests
.gitignore
arith_map.v
brams.txt
brams_bb.v
brams_init.py
brams_map.v
cells.box
cells.lut Update LUT delays 2019-04-10 08:49:39 -07:00
cells_map.v Fix cells_map.v some more 2019-04-11 10:48:14 -07:00
cells_sim.v Add abc_box_id attribute to MUXF7/F8 cells 2019-04-15 22:25:09 -07:00
cells_xtra.sh Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra. 2019-04-12 09:35:15 -07:00
cells_xtra.v Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra. 2019-04-12 09:35:15 -07:00
drams.txt
drams_map.v
ff_map.v
lut_map.v
Makefile.inc
synth_xilinx.cc Add support for synth_xilinx -abc9 and ignore abc9 -dress opt 2019-04-12 12:28:37 -07:00