Eddie Hung 1ec949d5ed Tidy up		2019-04-10 09:02:42 -07:00
..
tests	Improved xilinx "bram1" test	2015-04-09 17:12:12 +02:00
.gitignore	Added support for initialized xilinx brams	2015-04-06 17:07:10 +02:00
arith_map.v	Changes required for VPR place and route synth_xilinx.	2019-03-01 12:02:27 -08:00
brams.txt	Added read-enable to memory model	2015-09-25 12:23:11 +02:00
brams_bb.v	Added Xilinx bram black-box modules	2015-04-06 08:44:30 +02:00
brams_init.py	Squelch trailing whitespace, including meta-whitespace	2018-03-11 16:03:41 +01:00
brams_map.v	Revert BRAM WRITE_MODE changes.	2019-03-04 09:22:22 -08:00
cells.box	Add delays to cells.box	2019-04-09 14:32:10 -07:00
cells.lut	Update LUT delays	2019-04-10 08:49:39 -07:00
cells_map.v	Tidy up	2019-04-10 09:02:42 -07:00
cells_sim.v	Revert FF models to include IS_x_INVERTED parameters.	2019-03-01 14:41:21 -08:00
cells_xtra.sh	xilinx: Add keep attribute where appropriate	2019-03-22 13:57:17 +00:00
cells_xtra.v	xilinx: Add keep attribute where appropriate	2019-03-22 13:57:17 +00:00
drams.txt	Added memory_bram "make_outreg" feature	2015-04-09 16:08:54 +02:00
drams_map.v	Xilinx DRAMS: RAM64X1D, RAM128X1D	2015-04-09 13:37:07 +02:00
ff_map.v	Changes required for VPR place and route synth_xilinx.	2019-03-01 12:02:27 -08:00
lut_map.v	Changes required for VPR place and route synth_xilinx.	2019-03-01 12:02:27 -08:00
Makefile.inc	Add cells.lut to techlibs/xilinx/	2019-04-09 14:33:37 -07:00
synth_xilinx.cc	Move map_cells to before map_luts	2019-04-10 08:50:31 -07:00