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Code Activity
13641 commits 94 branches 53 tags 44 MiB
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287 commits

Author SHA1 Message Date
Eddie Hung
3df869cc7c Add testcase from #1459 2020-01-06 16:22:22 -08:00
Eddie Hung
6e866030c2 Combine tests to check multiple clock domains 2020-01-02 14:38:59 -08:00
Eddie Hung
b454735bea Merge remote-tracking branch 'origin/master' into xaig_dff 2020-01-02 12:44:06 -08:00
Eddie Hung
9e5ff30d05
Merge pull request #1606 from YosysHQ/eddie/improve_tests 
Fix a few issues in tests/arch/*
 2020-01-01 13:31:46 -08:00
Eddie Hung
52fe1e0c44 Revert insertion of 'reg', leave note behind 2020-01-01 09:05:46 -08:00
Miodrag Milanovic
a1344ec06e Added a test case 2020-01-01 16:24:30 +01:00
Eddie Hung
713484fa66 Do not do call equiv_opt when no sim model exists 2019-12-31 18:40:30 -08:00
Eddie Hung
a59016b146 Fix warnings 2019-12-31 18:40:11 -08:00
Eddie Hung
c082329af3 Call equiv_opt with -multiclock and -assert 2019-12-31 18:39:32 -08:00
Eddie Hung
ccc0a740d2 Add some abc9 dff tests 2019-12-31 16:16:05 -08:00
Eddie Hung
0c4be94a02 Add -D DFF_MODE to abc9_map test 2019-12-30 20:13:25 -08:00
Eddie Hung
405e974fe5 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-30 14:31:42 -08:00
Miodrag Milanović
c0a17c2457
Merge pull request #1589 from YosysHQ/iopad_default 
Make iopad option default for all xilinx flows
 2019-12-30 20:34:31 +01:00
Eddie Hung
c2c74f9bb0
Merge pull request #1599 from YosysHQ/eddie/retry_1588 
Retry #1588 -- "write_xaiger: only instantiate each whitebox cell type once"
 2019-12-30 10:01:02 -08:00
Miodrag Milanovic
f9749c202c Fix new tests 2019-12-28 16:43:19 +01:00
Miodrag Milanovic
8c3de1d4bd Merge remote-tracking branch 'origin/master' into iopad_default 2019-12-28 16:23:31 +01:00
Miodrag Milanovic
a82c701668 Make test without iopads 2019-12-28 16:22:24 +01:00
Miodrag Milanovic
509da7ed1a Revert "Fix xilinx tests, when iopads are default" 
This reverts commit 477e43d921.
 2019-12-28 16:12:45 +01:00
Eddie Hung
011f749ecf Update resource count 2019-12-28 02:15:11 -08:00
Eddie Hung
d45869855c Add #1598 testcase 2019-12-27 16:44:57 -08:00
Eddie Hung
2e21aa59a2 Add DSP cascade tests 2019-12-23 14:58:06 -08:00
Marcin Kościelnicki
666c6128a9 xilinx_dsp: Initial DSP48A/DSP48A1 support. 2019-12-22 20:51:14 +01:00
Miodrag Milanovic
436fea9e69 Addressed review comments 2019-12-21 20:23:23 +01:00
Miodrag Milanovic
477e43d921 Fix xilinx tests, when iopads are default 2019-12-21 13:18:44 +01:00
Eddie Hung
94f15f023c Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-19 10:29:40 -08:00
Marcin Kościelnicki
f382164d6e tests/xilinx: fix flaky mux test 2019-12-18 15:53:29 +01:00
Marcin Kościelnicki
a235250403 xilinx: Add xilinx_dffopt pass (#1557) 2019-12-18 13:43:43 +01:00
Marcin Kościelnicki
aff6ad1ce0 xilinx: Improve flip-flop handling. 
This adds support for infering more kinds of flip-flops:

- FFs with async set/reset and clock enable
- FFs with sync set/reset
- FFs with sync set/reset and clock enable

Some passes have been moved (and some added) in order for dff2dffs to
work correctly.

This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop
capabilities (though not latch capabilities).  Older FPGAs also support
having both a set and a reset input, which will be handled at a later
data.
 2019-12-18 13:43:43 +01:00
Eddie Hung
a73f96594f
Merge pull request #1574 from YosysHQ/eddie/xilinx_lutram 
xilinx: add LUTRAM rules for RAM32M, RAM64M
 2019-12-16 21:48:21 -08:00
Eddie Hung
378d9e6e0c Add another test 2019-12-16 13:57:55 -08:00
Eddie Hung
db0003410f Accidentally commented out tests 2019-12-16 13:31:47 -08:00
Eddie Hung
5a00d5578c Add unconditional match blocks for force RAM 2019-12-16 13:31:15 -08:00
Eddie Hung
e990c013c5 Merge blockram tests 2019-12-16 13:01:51 -08:00
Diego H
87e21b0122 Fixing compiler warning/issues. Moving test script to the correct place 2019-12-16 10:23:45 -06:00
Diego H
f3f59910eb Removing fixed attribute value to !ramstyle rules 2019-12-15 23:51:58 -06:00
Diego H
b35559fc33 Merging attribute rules into a single match block; Adding tests 2019-12-15 23:33:09 -06:00
Eddie Hung
a5764a1236 Disable RAM16X1D test 2019-12-13 10:28:13 -08:00
Diego H
1c96345587 Renaming BRAM memory tests for the sake of uniformity 2019-12-13 09:33:18 -06:00
Eddie Hung
d0ee4cd88f Remove extraneous synth_xilinx call 2019-12-12 19:00:26 -08:00
Eddie Hung
01116f0f0a Add tests for these new models 2019-12-12 18:52:48 -08:00
Eddie Hung
037d1a03df Add #1460 testcase 2019-12-12 17:49:55 -08:00
Eddie Hung
caab66111e Rename memory tests to lutram, add more xilinx tests 2019-12-12 17:44:37 -08:00
Diego H
751a18d7e9 Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1 test. 2019-12-12 17:32:58 -06:00
Eddie Hung
bea15b537b Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-12 14:57:17 -08:00
Eddie Hung
47ac1b01e6 Add test 2019-12-12 14:43:13 -08:00
Diego H
e33f407655 Adding a note (TODO) in the memory_params.ys check file 2019-12-12 16:06:46 -06:00
Diego H
937ec1ee78 Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1 2019-12-12 13:50:36 -06:00
Eddie Hung
7e5602ad17
Merge pull request #1545 from YosysHQ/eddie/ice40_wrapcarry_attr 
Preserve SB_CARRY name and attributes when using $__ICE40_CARRY_WRAPPER
 2019-12-09 17:38:48 -08:00
Eddie Hung
eff858cd33 unmap $__ICE40_CARRY_WRAPPER in test 2019-12-09 14:20:35 -08:00
Eddie Hung
e05372778a ice40_wrapcarry to really preserve attributes via -unwrap option 2019-12-09 11:48:28 -08:00