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yosys/tests/arch
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Marcin Kościelnicki aff6ad1ce0 xilinx: Improve flip-flop handling. 
This adds support for infering more kinds of flip-flops:

- FFs with async set/reset and clock enable
- FFs with sync set/reset
- FFs with sync set/reset and clock enable

Some passes have been moved (and some added) in order for dff2dffs to
work correctly.

This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop
capabilities (though not latch capabilities).  Older FPGAs also support
having both a set and a reset input, which will be handled at a later
data.
2019-12-18 13:43:43 +01:00
..
anlogic Rename memory tests to lutram, add more xilinx tests 2019-12-12 17:44:37 -08:00
common Merge pull request #1574 from YosysHQ/eddie/xilinx_lutram 2019-12-16 21:48:21 -08:00
ecp5 Rename memory tests to lutram, add more xilinx tests 2019-12-12 17:44:37 -08:00
efinix Rename memory tests to lutram, add more xilinx tests 2019-12-12 17:44:37 -08:00
gowin Rename memory tests to lutram, add more xilinx tests 2019-12-12 17:44:37 -08:00
ice40 Rename memory tests to lutram, add more xilinx tests 2019-12-12 17:44:37 -08:00
xilinx xilinx: Improve flip-flop handling. 2019-12-18 13:43:43 +01:00
run-test.sh Add simcells.v, simlib.v, and some output 2019-06-27 11:13:49 -07:00