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287 commits

Author SHA1 Message Date
KrystalDelusion
8f6a06951c Fix for sync_ram_sdp not being final module 
Explicitly declare -top in synth_intel_alm.
 2023-02-21 05:23:16 +13:00
KrystalDelusion
af1b9c9e07 Tests for ram_style = "huge" 
iCE40 SPRAM and Xilinx URAM
 2023-02-21 05:23:15 +13:00
KrystalDelusion
de2f140c09 Testing TDP synth mapping 
New common sync_ram_tdp.
Used in ecp5 and gatemate mem*.ys.
 2023-02-21 05:23:15 +13:00
KrystalDelusion
48f4e09202 Asymmetric port ram tests with Xilinx 
Uses verilog code from User Guide 901 (2021.1)
 2023-02-21 05:23:14 +13:00
KrystalDelusion
ac5fa9a838 Addings tests for #1836 and #3205 2023-02-21 05:23:14 +13:00
gatecat
b6467f0801 fabulous: Allow adding extra custom prims and map rules 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-11-17 13:34:58 +01:00
gatecat
f111bbdf40 fabulous: improvements to the pass 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-11-17 13:34:58 +01:00
Jannis Harder
0113f44faa Reenable existing equiv_opt tests 2022-10-07 16:04:51 +02:00
Jannis Harder
81906aa627 Fix tests for check in equiv_opt 2022-10-07 16:04:51 +02:00
Miodrag Milanovic
f4a1906721 support file locations containing spaces 2022-08-08 20:30:50 +02:00
gatecat
48efc9b75c gatemate: Add test for LUT tree mapping 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-06-27 10:09:48 +01:00
Marcelina Kościelnicka
9d11575856 efinix: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
Marcelina Kościelnicka
d7dc2313b9 ice40: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
Marcelina Kościelnicka
3b2f95953c xilinx: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
Marcelina Kościelnicka
0a8eaca322 nexus: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
Marcelina Kościelnicka
a04b025abf ecp5: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
Lofty
9f7a55c99f intel_alm: M10K write-enable is negative-true 2022-03-09 20:18:06 +00:00
Marcelina Kościelnicka
f61f2a4078 gowin: Fix LUT RAM inference, add more models. 2022-02-09 09:04:34 +01:00
Icenowy Zheng
c2b7ad3b28 anlogic: support BRAM mapping 
Anlogic FPGAs all have two kinds of BRAMs, one is 9bit*1K when being
true dual port (or 18bit*512 when simple dual port), the other is
16bit*2K.

Supports mapping of these two kinds of BRAMs. 9Kbit BRAM in SDP mode and
32Kbit BRAM with 8bit width are not support yet.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
 2021-12-17 20:28:22 +08:00
Claire Xenia Wolf
d6e4d3f1ba Fix the tests we just broke 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-12-10 00:22:37 +01:00
Miodrag Milanovic
d65942b9ac Add gitignore for gatemate 2021-12-03 09:56:37 +01:00
Patrick Urban
81964d6d6f synth_gatemate: Update pass 
* remove `write_edif` and `write_blif` options
* remove redundant `abc` call before muxcover
* update style
 2021-11-13 21:53:25 +01:00
Patrick Urban
97d03c2b3b synth_gatemate: Apply new test practice with assert-max 2021-11-13 21:53:25 +01:00
Patrick Urban
76bf96d310 synth_gatemate: Fix fsm test 2021-11-13 21:53:25 +01:00
Patrick Urban
acb993b27b Allow initial blocks to be disabled during tests 
Wrap initial blocks with a NO_INIT so that tests for archs without register initialization feature don't fail.
 2021-11-13 21:53:25 +01:00
Patrick Urban
240d289fff synth_gatemate: Initial implementation 
Signed-off-by: Patrick Urban <patrick.urban@web.de>
 2021-11-13 21:53:25 +01:00
Marcelina Kościelnicka
15b0d717ed iopadmap: Add native support for negative-polarity output enable. 2021-11-09 15:40:16 +01:00
Marcelina Kościelnicka
4e70c30775 FfData: some refactoring. 
- FfData now keeps track of the module and underlying cell, if any (so
  calling emit on FfData created from a cell will replace the existing cell)
- FfData implementation is split off to its own .cc file for faster
  compilation
- the "flip FF data sense by inserting inverters in front and after"
  functionality that zinit uses is moved onto FfData class and beefed up
  to have dffsr support, to support more use cases
 2021-10-07 04:24:06 +02:00
Eddie Hung
f03e2c30aa
abc9: replace cell type/parameters if derived type already processed (#2991) 
* Add close bracket

* Add testcase

* Replace cell type/param if in unmap_design

* Improve abc9_box error message too

* Update comment as per review
 2021-09-09 10:05:55 -07:00
Pepijn de Vos
c2d358484f
Gowin: deal with active-low tristate (#2971) 
* deal with active-low tristate

* remove empty port

* update sim models

* add expected lut1 to tests
 2021-08-20 21:21:06 +02:00
Marcelina Kościelnicka
b98376884e test/arch/{ecp5,ice40}/memories.ys: Use read_verilog -defer. 
These parts keep rereading a Verilog module, then using chparam
to test it with various parameter combinations.  Since the default
parameters are on the large side, this spends a lot of time
needlessly elaborating the default parametrization that will then
be discarded.  Fix it with -deref and manual hierarchy call.

Shaves 30s off the test time on my machine.
 2021-08-11 14:52:38 +02:00
Marcelina Kościelnicka
fd79217763 Add v2 memory cells. 2021-08-11 13:34:10 +02:00
Marcelina Kościelnicka
54e75129e5 opt_lut: Allow more than one -dlogic per cell type. 
Fixes #2061.
 2021-07-29 17:30:07 +02:00
Claire Xenia Wolf
92e705cb51 Fix files with CRLF line endings 2021-06-09 12:16:33 +02:00
Marcelina Kościelnicka
18806f1ef6 memory_bram: Reuse extract_rdff helper for make_outreg. 
Also properly skip read ports with init value or reset when not making
use of make_outreg.  Proper support for matching those will land later.
 2021-05-25 22:42:03 +02:00
gatecat
34a08750fa intel_alm: Fix illegal carry chains 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 22:37:06 +01:00
gatecat
eb106732d9 intel_alm: Add global buffer insertion 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 22:37:06 +01:00
gatecat
5dba138c87 intel_alm: Add IO buffer insertion 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 22:37:06 +01:00
Claire Xenia Wolf
8aee80040d Add default assignments to SB_LUT4 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-04-20 12:46:21 +02:00
Lofty
dce037a62c quicklogic: ABC9 synthesis 2021-04-17 20:54:58 +02:00
Marcelina Kościelnicka
4a35f244aa quicklogic: Add .gitignore file for test outputs. 2021-03-23 17:35:00 +01:00
Lofty
f4298b057a quicklogic: PolarPro 3 support 
Co-authored-by: Grzegorz Latosiński <glatosinski@antmicro.com>
Co-authored-by: Maciej Kurc <mkurc@antmicro.com>
Co-authored-by: Tarachand Pagarani <tpagarani@quicklogic.com>
Co-authored-by: Lalit Sharma <lsharma@quicklogic.com>
Co-authored-by: kkumar23 <kkumar@quicklogic.com>
 2021-03-18 13:28:16 +01:00
Marcelina Kościelnicka
8740fdf1d7 ast: Use better parameter serialization for paramod names. 
Calling log_signal is problematic for several reasons:

- with recent changes, empty string is serialized as { }, which violates
  the "no spaces in IdString" rule
- the type (plain / real / signed / string) is dropped, wrongly conflating
  functionally different values and potentially introducing a subtle
  elaboration bug

Instead, use a custom simple serialization scheme.
 2021-03-18 00:52:00 +01:00
gatecat
cae905f551 Blackbox all whiteboxes after synthesis 
This prevents issues like processes in whiteboxes triggering an error in
the JSON backend.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-17 21:07:20 +00:00
William D. Jones
ae07298a6b machxo2: Switch to LUT4 sim model which propagates less undefined/don't care values. 2021-02-23 17:39:58 +01:00
William D. Jones
353ace5034 machxo2: Update tribuf test to reflect active-low OE. 2021-02-23 17:39:58 +01:00
William D. Jones
c31b17a2e2 machxo2: Add believed-to-be-correct tribuf test. 2021-02-23 17:39:58 +01:00
William D. Jones
c7aaa88f58 machxo2: Add passing fsm, mux, and shifter tests. 2021-02-23 17:39:58 +01:00
William D. Jones
453904dd00 machxo2: Add add_sub test. Fix tests to include FACADE_IO primitives. 2021-02-23 17:39:58 +01:00
William D. Jones
19b043344c machxo2: Add dffe test. 2021-02-23 17:39:58 +01:00