mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-24 17:45:33 +00:00
Code Activity
13896 commits 96 branches 53 tags 45 MiB
Commit graph

4113 commits

Author SHA1 Message Date
Clifford Wolf
edd297fb1c Fix iopadmap for cases where IO pins already have buffers on them 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-15 13:13:43 +02:00
Aman Goel
8b9a8c7f91 Minor correction 
Minor typo error correction in -expose with setundef
 2018-05-14 18:58:49 -04:00
Aman Goel
b4a303a1b7 Corrections to option -expose in setundef pass 2018-05-13 20:13:54 -04:00
Aman Goel
9286acb687 Add option -expose to setundef pass 
Option -expose converts undriven wires to inputs.

Example usage: setundef -undriven -expose [selection]
 2018-05-13 16:53:35 -04:00
Clifford Wolf
0fad1570b5 Some cleanups in setundef.cc 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-13 16:36:12 +02:00
Christian Krämer
c1ecb1b2f1 Add "#ifdef __FreeBSD__" 
(Re-commit e3575a8 with corrected author field)
 2018-05-13 13:08:26 +02:00
Clifford Wolf
1167538d26 Revert "Add "#ifdef __FreeBSD__"" 
This reverts commit e3575a86c5.
 2018-05-13 13:06:36 +02:00
Clifford Wolf
587056447e Add optimization of tristate buffer with constant control input 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-12 15:18:27 +02:00
Clifford Wolf
11406a8082 Add "hierarchy -simcheck" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-12 13:59:13 +02:00
Johnny Sorocil
e3575a86c5 Add "#ifdef __FreeBSD__" 2018-05-05 13:02:44 +02:00
Clifford Wolf
145c685de0 Add ABC FAQ to "help abc" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-04 21:59:31 +02:00
Clifford Wolf
a572b49538 Replace -ignore_redef with -[no]overwrite 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-03 15:25:59 +02:00
Clifford Wolf
705c366a91 Added missing dont_use handling for SR FFs to dfflibmap 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-04-05 11:01:45 +02:00
Clifford Wolf
665eec3d53 Removed $timescale from "sat" command VCD writer 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-29 12:38:41 +02:00
Clifford Wolf
ee3c12d6d9 Chenged "extensions_map" to "extensions_list" in hierarchy.cc 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-27 14:12:57 +02:00
Sergi Granell
f93f8aaa11 passes/hierarchy: Reduce code duplication in expand_module 
This also makes it easier to add new file extensions support.

Signed-off-by: Sergi Granell <xerpi.g.12@gmail.com>
 2018-03-27 09:35:20 +02:00
Clifford Wolf
491c352da7 Add .sv support to "hierarchy -libdir" 2018-03-26 21:19:00 +02:00
Clifford Wolf
08225f49a4 Add "expose -input" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-12 13:52:52 +01:00
Clifford Wolf
83ffb23739 Add "setundef -undef" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-12 13:52:35 +01:00
Clifford Wolf
a74f805ba0 Fix handling of src attributes in flatten 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-10 13:55:30 +01:00
Clifford Wolf
73c01dca65 Add "memory_nordff" pass 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-06 23:31:51 +01:00
Clifford Wolf
61a9e2eeb3 Fix connwrappers help message 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-04 22:54:34 +01:00
Clifford Wolf
d31584c649 Add $dlatchsr support to clk2fflogic 2018-02-26 12:20:28 +01:00
Clifford Wolf
fba499b866 Fix opt_rmdff handling of $dlatchsr 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-02-26 11:46:05 +01:00
Clifford Wolf
eb67a7532b Add $allconst and $allseq cell types 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-02-23 13:14:47 +01:00
Clifford Wolf
717abc93a8 Recognize stand-alone obj pattern even when it contains a slash 2018-02-13 14:55:24 +01:00
Clifford Wolf
9337e4999d Improve log messages in equiv_make 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-01-19 16:20:40 +01:00
Clifford Wolf
9ac560f5d3 Add "dffinit -highlow" and fix synth_intel 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-01-09 18:42:19 +01:00
Clifford Wolf
a96c775a73 Add support for "yosys -E" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-01-07 16:36:13 +01:00
Clifford Wolf
446ccf1f05 Bugfix in hierarchy blackbox module port width handling 2018-01-07 16:35:22 +01:00
Clifford Wolf
c80315cea4 Bugfix in hierarchy handling of blackbox module ports 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-01-05 13:28:45 +01:00
Clifford Wolf
fefb652d56
Merge pull request #480 from Fatsie/liberty_value_expression 
Value of properties can be expression.
 2018-01-04 13:30:00 +01:00
Clifford Wolf
2d140a44eb Temporarily derive blackbox modules in hierarchy to evaluate port widths 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-01-04 13:23:29 +01:00
Staf Verhaegen
92eb841f0a Value of properties can be expression. 
Example found in the 2007.03 Liberty Reference Manual that was also found
in the wild:

    input_voltage(CMOS) {
        vil : 0.3 * VDD ;
        vih : 0.7 * VDD ;
        vimin : -0.5 ;
        vimax : VDD + 0.5 ;
    }

Current implementation just parses the expression but no interpretation is done.
 2018-01-03 21:37:17 +00:00
Clifford Wolf
6132e6e72a Fix a bug in clk2fflogic memory handling 2017-12-14 03:05:55 +01:00
Clifford Wolf
590e6961cb Add clk2fflogic memory support 2017-12-14 02:07:31 +01:00
Clifford Wolf
88182e46d7 Check for memories in clk2fflogic 2017-12-13 19:14:34 +01:00
Clifford Wolf
ca2adc30c9 Add warnings for driver-driver conflicts between FFs (and other cells) and constants 2017-12-12 17:13:27 +01:00
Clifford Wolf
9ae25039fb Add support for editline as replacement for readline 2017-11-08 02:55:00 +01:00
Clifford Wolf
4f31cb6dad Add "ltp" command 2017-10-31 12:40:25 +01:00
Clifford Wolf
c238f45ecf Fix memory corruption bug in opt_rmdff 2017-10-26 18:02:15 +02:00
Clifford Wolf
1e502ef5a0 Fix typo in opt_clean log message 2017-10-26 18:01:48 +02:00
Kaj Tuomi
e558b3284b Fix input vector for reduce cells. Infinite loop fixed. 2017-10-17 09:58:01 +03:00
Clifford Wolf
716dbc9274 Revert 90be0d8 as it causes endless loops for some designs 2017-10-14 11:57:25 +02:00
Kaj Tuomi
90be0d800b Fix input vector for reduce cells. 2017-10-12 13:05:10 +03:00
Clifford Wolf
7c57d8fbb4 Rewrite ABC output to include proper net names in timing report 2017-10-10 13:32:58 +02:00
Clifford Wolf
3f22f48eeb Add blackbox command 2017-10-04 18:30:42 +02:00
Andrew Zonenberg
2b65b65d70 Added missing "break" 2017-09-15 17:54:52 -07:00
Andrew Zonenberg
7b3966714c Implemented off-chain support for extract_reduce 2017-09-15 13:59:18 -07:00
Andrew Zonenberg
3404934c9c extract_reduce now only removes the head of the chain, relying on "clean" to delete upstream cells. Added "-allow-off-chain" flag, but it's currently ignored. 2017-09-15 13:59:05 -07:00