mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-05 17:14:08 +00:00
Code Activity

Bugfix in hierarchy blackbox module port width handling

Browse source
This commit is contained in:
Clifford Wolf 2018-01-07 16:35:22 +01:00
parent b557989576
commit 446ccf1f05
1 changed files with 2 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
passes/hierarchy/hierarchy.cc
View file

@ -621,8 +621,9 @@ struct HierarchyPass : public Pass {
}
std::set<Module*> blackbox_derivatives;
std::vector<Module*> design_modules = design->modules();
for (auto module : design->modules())
for (auto module : design_modules)
for (auto cell : module->cells())
{
Module *m = design->module(cell->type);