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	Fix input vector for reduce cells.
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			@ -88,6 +88,7 @@ struct OptReduceWorker
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		RTLIL::SigSpec new_sig_a(new_sig_a_bits);
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		if (new_sig_a != sig_a || sig_a.size() != cell->getPort("\\A").size()) {
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			new_sig_a.sort_and_unify();
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			log("    New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a));
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			did_something = true;
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			total_count++;
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