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13474 commits 94 branches 53 tags 44 MiB
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1806 commits

Author SHA1 Message Date
Udi Finkelstein
95241c8f4d Yosys can now parse https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/primitives.v , 
(specify block ignored).
Must use 'read_verilog -defer' due to a parameter not assigned a default value.
 2018-08-20 00:08:08 +03:00
Clifford Wolf
e343f3e6d4 Add "verific -set-<severity> <msg_id>.." 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-16 11:49:17 +02:00
Clifford Wolf
0899a53bee Verific workaround for VIPER ticket 13851 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-16 11:31:19 +02:00
Udi Finkelstein
28cfc75a90 A few minor enhancements to specify block parsing. 
Just remember specify blocks are parsed but ignored.
 2018-08-15 20:14:52 +03:00
Clifford Wolf
67b1026297
Merge pull request #591 from hzeller/virtual-override 
Consistent use of 'override' for virtual methods in derived classes.
 2018-08-15 14:05:38 +02:00
Clifford Wolf
d8e40c75eb
Merge pull request #590 from hzeller/remaining-file-error 
Fix remaining log_file_error(); emit dependent file references in new…
 2018-08-15 14:01:34 +02:00
Clifford Wolf
3d27c1cc80
Merge pull request #513 from udif/pr_reg_wire_error 
Add error checking for reg/wire/logic misuse - PR now passes 'make test' (plus a new test)
 2018-08-15 13:35:41 +02:00
Clifford Wolf
d71529baa1
Merge pull request #562 from udif/pr_fix_illegal_port_decl 
Detect illegal port declaration, e.g input/output/inout keyword must …
 2018-08-15 13:14:23 +02:00
Clifford Wolf
93efbd5d15 Fixed use of char array for string in blifparse error handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-08 19:41:47 +02:00
litghost
219f1e9fc9 Report error reason on same line as syntax error. 
Signed-off-by: litghost <537074+litghost@users.noreply.github.com>
 2018-08-08 10:22:55 -07:00
litghost
475c2af812 Use log_warning which does not immediately terminate. 2018-08-03 08:05:45 -07:00
litghost
f42d6a9c93 Add BLIF parsing support for .conn and .cname 2018-08-02 14:36:56 -07:00
Clifford Wolf
e275692e84 Verific: Produce errors for instantiating unknown module 
Because if the unknown module is connected to any constants, Verific will
actually break all constants in the same module, even if they have nothing
to do structurally with that instance of an unknown module.

Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-22 18:44:05 +02:00
Henner Zeller
3aa4484a3c Consistent use of 'override' for virtual methods in derived classes. 
o Not all derived methods were marked 'override', but it is a great
  feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
  provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
  use the plain keyword going forward now that C++11 is established)
 2018-07-20 23:51:06 -07:00
Henner Zeller
3101b9b8c9 Fix remaining log_file_error(); emit dependent file references in new line. 
There are some places that reference dependent file locations ("this function was
called from ..."). These are now in a separate line for ease of jumping to
it with the editor (behaves similarly to compilers that emit dependent
messages).
 2018-07-20 18:52:52 -07:00
Henner Zeller
68b5d0c3b1 Convert more log_error() to log_file_error() where possible. 
Mostly statements that span over multiple lines and haven't been
caught with the previous conversion.
 2018-07-20 09:37:44 -07:00
Henner Zeller
b5ea598ef6 Use log_file_warning(), log_file_error() functions. 
Wherever we can report a source-level location.
 2018-07-20 08:19:06 -07:00
Henner Zeller
1a60126a34 Provide source-location logging. 
o Provide log_file_warning() and log_file_error() that prefix the log
  message with <filename>:<lineno>: to be easily picked up by IDEs that
  need to step through errors.
o Simplify some duplicate logging code in kernel/log.cc
o Use the new log functions in genrtlil.
 2018-07-19 10:22:02 -07:00
Clifford Wolf
65234d4b24 Fix handling of eventually properties in verific importer 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-17 12:43:30 +02:00
Clifford Wolf
5041ed2f7d Fix verific -vlog-incdir and -vlog-libdir handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-16 18:47:42 +02:00
Clifford Wolf
f897af626d Fix "read -incdir" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-16 16:48:09 +02:00
Clifford Wolf
f39b897545 Add "read -incdir" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-16 15:32:26 +02:00
Clifford Wolf
8b92ddb9d2 Fix verific eventually handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-29 19:24:58 +02:00
Clifford Wolf
0404cf61d5 Add verific support for eventually properties 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-29 19:21:04 +02:00
Clifford Wolf
ebf0f003d3 Add "verific -formal" and "read -formal" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-29 10:02:27 +02:00
Clifford Wolf
afedb2d03e Add "read -sv -D" support 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-28 23:58:15 +02:00
Clifford Wolf
07e616900c Add "read -undef" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-28 23:43:38 +02:00
Clifford Wolf
fe2ee833e1 Fix handling of signed memories 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-28 16:57:03 +02:00
Clifford Wolf
848c3c5c88 Add YOSYS_NOVERIFIC env variable for temporarily disabling verific 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-22 20:40:22 +02:00
Clifford Wolf
d412b17259 Add simplified "read" command, enable extnets in implicit Verific import 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-21 16:56:55 +02:00
Clifford Wolf
5f2bc1ce76 Add automatic verific import in hierarchy command 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-20 23:45:01 +02:00
Clifford Wolf
0ff0ce4973 Bugfix in liberty parser (as suggested by aiju in #569) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-15 18:56:44 +02:00
Udi Finkelstein
8b7580b0a1 Detect illegal port declaration, e.g input/output/inout keyword must be the first. 2018-06-06 22:27:25 +03:00
Udi Finkelstein
73d426bc87 Modified errors into warnings 
No longer false warnings for memories and assertions
 2018-06-05 18:03:22 +03:00
Clifford Wolf
4372cf690d Add (* gclk *) attribute support 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-01 13:25:42 +02:00
Clifford Wolf
9a946c207f Add comment to VIPER #13453 work-around 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-28 13:36:35 +02:00
Clifford Wolf
001c9f1d45 Fix Verific handling of single-bit anyseq/anyconst wires 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-25 15:41:45 +02:00
Clifford Wolf
251562a491 Fix VerificClocking for cases where Verific generates chains of PRIM_SVA_POSEDGE 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-24 18:13:38 +02:00
Clifford Wolf
4d645f0fce Fix verific handling of anyconst/anyseq attributes 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-24 17:07:06 +02:00
Jim Paris
4a229e5b95 Support SystemVerilog `` extension for macros 2018-05-17 00:09:56 -04:00
Jim Paris
872d8d49e9 Skip spaces around macro arguments 2018-05-17 00:06:49 -04:00
Clifford Wolf
a7281930c5 Fix handling of anyconst/anyseq attrs in VHDL code via Verific 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-15 19:27:00 +02:00
Sergiusz Bazanski
7d076f071e Also interpret '&' in liberty functions 2018-05-12 20:55:31 +02:00
Clifford Wolf
24e6401617 Further improve handling of zero-length SVA consecutive repetition 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-05 14:32:04 +02:00
Clifford Wolf
3e67497ec2 Fix handling of zero-length SVA consecutive repetition 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-05 13:58:01 +02:00
Clifford Wolf
a572b49538 Replace -ignore_redef with -[no]overwrite 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-03 15:25:59 +02:00
Dan Gisselquist
e060375f23 Support more character literals 2018-05-03 12:35:01 +02:00
Clifford Wolf
2d7f3123f0 Add statement labels for immediate assertions 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-04-13 11:52:28 +02:00
Clifford Wolf
66ffc99695 Allow "property" in immediate assertions 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-04-12 14:28:28 +02:00
Clifford Wolf
617c60cea6 Add PRIM_HDL_ASSERTION support to Verific importer 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-04-07 18:38:42 +02:00