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	Add "read -undef"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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					 1 changed files with 32 additions and 0 deletions
				
			
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			@ -1715,6 +1715,11 @@ struct VerificPass : public Pass {
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		log("Add Verilog defines. (The macros SYNTHESIS and VERIFIC are defined implicitly.)\n");
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		log("\n");
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		log("\n");
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		log("    verific -vlog-undef <macro>..\n");
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		log("\n");
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		log("Remove Verilog defines previously set with -vlog-define.\n");
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		log("\n");
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		log("\n");
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		log("    verific -import [options] <top-module>..\n");
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		log("\n");
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		log("Elaborate the design for the specified top modules, import to Yosys and\n");
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			@ -1828,6 +1833,14 @@ struct VerificPass : public Pass {
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			goto check_error;
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		}
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		if (GetSize(args) > argidx && args[argidx] == "-vlog-undef") {
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			for (argidx++; argidx < GetSize(args); argidx++) {
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				string name = args[argidx];
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				veri_file::UndefineMacro(name.c_str());
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			}
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			goto check_error;
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		}
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		if (GetSize(args) > argidx && (args[argidx] == "-vlog95" || args[argidx] == "-vlog2k" || args[argidx] == "-sv2005" ||
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				args[argidx] == "-sv2009" || args[argidx] == "-sv2012" || args[argidx] == "-sv"))
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		{
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			@ -2139,6 +2152,11 @@ struct ReadPass : public Pass {
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		log("\n");
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		log("Set global Verilog/SystemVerilog defines.\n");
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		log("\n");
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		log("\n");
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		log("    read -undef <macro>..\n");
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		log("\n");
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		log("Unset global Verilog/SystemVerilog defines.\n");
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		log("\n");
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	}
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	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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	{
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			@ -2200,6 +2218,20 @@ struct ReadPass : public Pass {
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			return;
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		}
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		if (args[1] == "-undef") {
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			if (use_verific) {
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				args[0] = "verific";
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				args[1] = "-vlog-undef";
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				Pass::call(design, args);
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			}
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			args[0] = "verilog_defines";
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			args.erase(args.begin()+1, args.begin()+2);
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			for (int i = 1; i < GetSize(args); i++)
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				args[i] = "-U" + args[i];
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			Pass::call(design, args);
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			return;
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		}
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		log_cmd_error("Missing or unsupported mode parameter.\n");
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	}
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} ReadPass;
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