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Fix handling of signed memories

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-06-28 16:57:03 +02:00
parent 848c3c5c88
commit fe2ee833e1
1 changed files with 3 additions and 0 deletions

3
frontends/ast/genrtlil.cc
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@ -1300,6 +1300,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(0);
cell->parameters["\\TRANSPARENT"] = RTLIL::Const(0);
if (!sign_hint)
is_signed = false;
return RTLIL::SigSpec(wire);
}