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Code Activity
9678 commits 95 branches 53 tags 45 MiB
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855 commits

Author SHA1 Message Date
Eddie Hung
ba2261e21a Move from cell attr to module attr 2019-08-19 11:18:33 -07:00
Eddie Hung
d81a090d89 Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro 2019-08-19 09:56:17 -07:00
Eddie Hung
e301440a0b Use attributes instead of params 2019-08-19 09:51:49 -07:00
Eddie Hung
24c934f1af Merge branch 'eddie/abc9_refactor' into xaig_dff 2019-08-16 16:51:22 -07:00
Eddie Hung
562c9e3624 Attach abc_scc_break, abc_carry_{in,out} attr to ports not modules 2019-08-16 15:40:53 -07:00
Eddie Hung
261daffd9d Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp 2019-08-15 12:19:47 -07:00
Marcin Kościelnicki
3c75a72feb move attributes to wires 2019-08-13 19:36:59 +00:00
Eddie Hung
ed4b2834ef Add assign PCOUT = P to DSP48E1 2019-08-13 12:19:26 -07:00
Marcin Kościelnicki
49765ec19e minor review fixes 2019-08-13 18:05:49 +00:00
Eddie Hung
2a1b98d478 Add DSP_A_MAXWIDTH_PARTIAL, refactor 2019-08-13 10:21:24 -07:00
David Shah
edff79a25a xilinx: Rework labels for faster Verilator testing 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-13 10:29:42 +01:00
Marcin Kościelnicki
c6d5b97b98 review fixes 2019-08-13 00:35:54 +00:00
Marcin Kościelnicki
f4c62f33ac Add clock buffer insertion pass, improve iopadmap. 
A few new attributes are defined for use in cell libraries:

- iopad_external_pin: marks PAD cell's external-facing pin.  Pad
  insertion will be skipped for ports that are already connected
  to such a pin.
- clkbuf_sink: marks an input pin as a clock pin, requesting clock
  buffer insertion.
- clkbuf_driver: marks an output pin as a clock buffer output pin.
  Clock buffer insertion will be skipped for nets that are already
  driven by such a pin.

All three are module attributes that should be set to a comma-separeted
list of pin names.

Clock buffer insertion itself works as follows:

1. All cell ports, starting from bottom up, can be marked as clock sinks
   (requesting clock buffer insertion) or as clock buffer outputs.
2. If a wire in a given module is driven by a cell port that is a clock
   buffer output, it is in turn also considered a clock buffer output.
3. If an input port in a non-top module is connected to a clock sink in a
   contained cell, it is also in turn considered a clock sink.
4. If a wire in a module is driven by a non-clock-buffer cell, and is
   also connected to a clock sink port in a contained cell, a clock
   buffer is inserted in this module.
5. For the top module, a clock buffer is also inserted on input ports
   connected to clock sinks, optionally with a special kind of input
   PAD (such as IBUFG for Xilinx).
6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit
   attribute is set on it.
 2019-08-13 00:16:38 +02:00
Eddie Hung
f890cfb63b Merge remote-tracking branch 'origin/master' into xc7dsp 2019-08-12 11:32:10 -07:00
Eddie Hung
0b5b56c1ec Pack partial-product adder DSP48E1 packing 2019-08-09 15:19:33 -07:00
Eddie Hung
1f722b3500 Remove signed from ports in +/xilinx/dsp_map.v 2019-08-08 16:33:20 -07:00
Eddie Hung
162eab6b74 Combine techmap calls 2019-08-08 10:55:48 -07:00
Eddie Hung
7160243874 Move xilinx_dsp to before alumacc 2019-08-08 10:45:56 -07:00
Eddie Hung
57b2e4b9c1 INMODE is 5 bits 2019-08-08 10:44:35 -07:00
Eddie Hung
13cc106cf7 Fix copy-pasta typo 2019-08-08 10:44:26 -07:00
David Shah
b8cd4ad64a DSP48E1 sim model: add SIMD tests 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 11:39:35 +01:00
David Shah
57aeb4cc01 DSP48E1 model: test CE inputs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 11:32:43 +01:00
David Shah
d60b3c0dc8 DSP48E1 sim model: fix seq tests and add preadder tests 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 11:18:37 +01:00
David Shah
e7dbe7bb3d DSP48E1 sim model: seq test working 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 10:52:04 +01:00
David Shah
f6605c7dc0 DSP48E1 sim model: Comb, no pre-adder, mode working 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 10:26:44 +01:00
David Shah
f0f352e971 [wip] sim model testing 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 10:05:11 +01:00
David Shah
ccfb4ff2a9 [wip] sim model testing 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 09:31:34 +01:00
Eddie Hung
48d0f99406 stoi -> atoi 2019-08-07 11:09:17 -07:00
David Shah
fe95807f16 [wip] DSP48E1 sim model improvements 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-07 13:09:12 +01:00
David Shah
c43b0c4b49 [wip] DSP48E1 sim model improvements 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-06 18:47:18 +01:00
David Shah
7a563d0b92 [wip] DSP48E1 sim model improvements 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-06 13:23:42 +01:00
Eddie Hung
fc0b5d5ab6 Change $__softmul back to $mul 2019-08-01 12:45:14 -07:00
Eddie Hung
ed303b07b7 Merge remote-tracking branch 'origin/master' into xc7dsp 2019-08-01 12:02:16 -07:00
Eddie Hung
66806085db RST -> RSTBRST for RAMB8BWER 2019-07-29 16:05:44 -07:00
David Shah
ab607e896e xilinx: Fix missing cell name underscore in cells_map.v 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-25 08:19:07 +01:00
Eddie Hung
601fac97e4 Add params 2019-07-18 21:02:49 -07:00
Eddie Hung
43616e1414 Update Makefile too 2019-07-18 14:51:55 -07:00
Eddie Hung
b97fe6e866 Work in progress for renaming labels/options in synth_xilinx 2019-07-18 14:20:43 -07:00
Eddie Hung
5562cb08a4 Use single DSP_SIGNEDONLY macro 2019-07-18 13:09:55 -07:00
Eddie Hung
e3f8e59f18 Make all operands signed 2019-07-17 14:25:40 -07:00
Eddie Hung
58e63feae1 Update comment 2019-07-17 13:26:17 -07:00
Eddie Hung
c501aa5ee8 Signedness 2019-07-16 15:54:27 -07:00
Eddie Hung
6390c535ba Revert drop down to 24x16 multipliers for all 2019-07-16 14:30:25 -07:00
Eddie Hung
569cd66764 Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp 2019-07-16 14:18:36 -07:00
Eddie Hung
5d1ce04381 Add support for {A,B,P}REG in DSP48E1 2019-07-16 14:05:50 -07:00
David Shah
d38df68d26 xilinx: Add correct signed behaviour to DSP48E1 model 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-16 17:53:08 +01:00
David Shah
95c8d27b0b xilinx: Treat DSP48E1 as 24x17 unsigned for now (actual behaviour is 25x18 signed) 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-16 16:47:53 +01:00
Eddie Hung
5f00d335d4 Oops forgot these files 2019-07-15 15:03:15 -07:00
Eddie Hung
0c7ee6d0fa Move DSP mapping back out to dsp_map.v 2019-07-15 14:18:44 -07:00
Eddie Hung
20e3d2d9b0 Move DSP48E1 model out of cells_xtra, initial multiply one in cells_sim 2019-07-15 11:13:22 -07:00