1335 commits

Author	SHA1	Message	Date
Clifford Wolf	cda37830b0	Add hack for handling SVA labels via Verific ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-03-07 10:52:44 -08:00
Clifford Wolf	52f80718a7	Merge pull request #848 from YosysHQ/clifford/fix763 ... Fix error for wire decl in always block, fixes 763	2019-03-02 16:32:58 -08:00
Clifford Wolf	ae9286386d	Only run derive on blackbox modules when ports have dynamic size ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-03-02 12:36:46 -08:00
Clifford Wolf	3a51714451	Fix error for wire decl in always block, fixes #763 ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-03-02 11:56:44 -08:00
Clifford Wolf	ce6695e22c	Fix $global_clock handling vs autowire ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-03-02 10:38:13 -08:00
Clifford Wolf	5d93dcce86	Fix $readmem[hb] for mem2reg memories, fixes #785 ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-03-02 09:58:20 -08:00
Clifford Wolf	7cfae2c52f	Use mem2reg on memories that only have constant-index write ports ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-03-01 13:35:09 -08:00
Clifford Wolf	60e3c38054	Improve "read" error msg ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-02-28 20:34:42 -08:00
Eddie Hung	f7c7003a19	Merge remote-tracking branch 'origin/master' into xaig	2019-02-26 13:16:03 -08:00
Eddie Hung	da076344cc	parse_xaiger() to really pass single and multi-bit inout tests	2019-02-26 12:04:45 -08:00
Eddie Hung	8f02c846f6	parse_xaiger() to cope with multi bit inouts	2019-02-26 11:37:34 -08:00
Eddie Hung	316232a7dd	parse_xaiger() to untransform $inout.out output ports	2019-02-25 18:40:23 -08:00
Eddie Hung	721f6a14fb	read_aiger to accept empty string for clk_name, passable only if no latches	2019-02-25 15:34:02 -08:00
Clifford Wolf	1816fe06af	Fix handling of defparam for when default_nettype is none ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-02-24 20:09:41 +01:00
Clifford Wolf	a516b4fb5a	Check if Verific was built with DB_PRESERVE_INITIAL_VALUE ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-02-24 19:51:30 +01:00
Eddie Hung	07036b8bf7	read_aiger to work with symbol table	2019-02-21 17:01:07 -08:00
Eddie Hung	085ed9f487	Add attribution	2019-02-21 14:40:13 -08:00
Eddie Hung	3307295488	Merge branch 'read_aiger' into xaig	2019-02-21 14:27:32 -08:00
Clifford Wolf	23148ffae1	Fixes related to handling of autowires and upto-ranges, fixes #814 ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-02-21 18:40:11 +01:00
Clifford Wolf	974927adcf	Fix handling of expression width in $past, fixes #810 ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-02-21 17:55:33 +01:00
Clifford Wolf	28fba903c5	Fix segfault in printing of some internal error messages ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-02-21 17:40:52 +01:00
Eddie Hung	9e299a0908	read_aiger to not do -purge for clean	2019-02-20 17:33:04 -08:00
Eddie Hung	32853b1f8d	lut/not/and suffix to be ${lut,not,and}	2019-02-20 16:30:30 -08:00
Eddie Hung	abc1c2672e	read_aiger to also rename 0 index lut when wideports	2019-02-20 16:17:22 -08:00
Eddie Hung	f9702a8abe	read_aiger: new naming fixes	2019-02-20 12:39:51 -08:00
Eddie Hung	83b66861e9	read_aiger to name wires with internal name, less likely to clash	2019-02-20 11:22:56 -08:00
Eddie Hung	7b026c4bc3	Same for ascii AIGERs too	2019-02-19 15:15:50 -08:00
Eddie Hung	d304882cba	read_aiger to cope with non-unique POs	2019-02-19 15:14:08 -08:00
Eddie Hung	e79df5e70e	read_aiger to create sane $lut names, and rename when renaming driving wire	2019-02-19 12:27:50 -08:00
Eddie Hung	0b1fc46ae3	Add comment	2019-02-19 10:24:55 -08:00
Eddie Hung	54f719f446	Get rid of boost dep, fix the FIXMEs for Win32?	2019-02-19 10:19:53 -08:00
Eddie Hung	843e7fc8a7	Fix for using POSIX basename	2019-02-19 09:02:37 -08:00
Eddie Hung	8e1dbfac3a	Missing OSX headers?	2019-02-17 20:59:53 -08:00
Eddie Hung	9268a271fb	read_aiger to ignore line after ands for ascii, not binary	2019-02-17 12:07:14 -08:00
Eddie Hung	03a533d102	Merge https://github.com/YosysHQ/yosys into read_aiger	2019-02-17 11:44:01 -08:00
Eddie Hung	82459c16c4	In read_xaiger, do not construct ConstEval for every LUT	2019-02-16 22:22:29 -08:00
Eddie Hung	f60cd4ff9b	read_aiger to ignore output = input of same wire; also create new output for different wire	2019-02-16 21:53:03 -08:00
Eddie Hung	1a25ec4baa	read_aiger to disable log_debug	2019-02-16 13:45:51 -08:00
Eddie Hung	8f36013fac	read_xaiger() to use f.read() not readsome()	2019-02-16 08:58:25 -08:00
Eddie Hung	7523c87780	read_aiger() to cope with constant outputs, mixed wideports, do cleaning	2019-02-16 08:44:11 -08:00
Eddie Hung	8d757224ee	read_aiger with more asserts, and call clean	2019-02-15 11:52:05 -08:00
Eddie Hung	c7ef3863f3	Leave FIXME for clean	2019-02-13 17:19:30 -08:00
Eddie Hung	396da54b52	Use module->addLut()	2019-02-13 17:08:32 -08:00
Eddie Hung	13bf036bd6	Use ConstEval to compute LUT masks	2019-02-13 17:00:00 -08:00
Eddie Hung	f0f5d8a5cc	Merge remote-tracking branch 'origin/read_aiger' into xaig	2019-02-13 14:09:36 -08:00
Eddie Hung	06cf0555ee	Merge https://github.com/YosysHQ/yosys into xaig	2019-02-13 14:08:31 -08:00
Clifford Wolf	807b3c7697	Fix sign handling of real constants ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-02-13 12:36:47 +01:00
Eddie Hung	e9df9a466a	Add support for read_aiger -wideports	2019-02-12 12:58:10 -08:00
Eddie Hung	06ba81d41f	Add support for read_aiger -map	2019-02-12 12:16:37 -08:00
Eddie Hung	77d3627753	Parse 'm' in xaiger	2019-02-12 09:36:22 -08:00