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Merge remote-tracking branch 'origin/read_aiger' into xaig

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This commit is contained in:
Eddie Hung 2019-02-13 14:09:36 -08:00
commit f0f5d8a5cc
4 changed files with 12 additions and 17 deletions
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13
frontends/aiger/aigerparse.cc
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@ -316,9 +316,7 @@ static RTLIL::Wire* createWireIfNotExists(RTLIL::Module *module, unsigned litera
}
log_debug("Creating %s = ~%s\n", wire_name.c_str(), wire_inv_name.c_str());
RTLIL::Cell *inv = module->addCell(stringf("\\n%d_not", variable), "$_NOT_"); // FIXME: is "_not" the right suffix?
inv->setPort("\\A", wire_inv);
inv->setPort("\\Y", wire);
module->addNotGate(stringf("\\n%d_not", variable), wire_inv, wire); // FIXME: is "_not" the right suffix?
return wire;
}
@ -409,7 +407,7 @@ void AigerReader::parse_aiger_ascii(bool create_and)
std::getline(f, line); // Ignore up to start of next line
// Parse AND
for (unsigned i = 0; i < A; ++i, ++line_count) {
for (unsigned i = 0; i < A; ++i) {
if (!(f >> l1 >> l2 >> l3))
log_error("Line %u cannot be interpreted as an AND!\n", line_count);
@ -419,14 +417,9 @@ void AigerReader::parse_aiger_ascii(bool create_and)
RTLIL::Wire *o_wire = createWireIfNotExists(module, l1);
RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2);
RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3);
RTLIL::Cell *and_cell = module->addCell(NEW_ID, "$_AND_");
and_cell->setPort("\\A", i1_wire);
and_cell->setPort("\\B", i2_wire);
and_cell->setPort("\\Y", o_wire);
module->addAndGate(NEW_ID, i1_wire, i2_wire, o_wire);
}
}
std::getline(f, line); // Ignore up to start of next line
}
static unsigned parse_next_delta_literal(std::istream &f, unsigned ref)