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687a36af38 · Merge pull request #5711 from YosysHQ/gowin_warning · Updated 2026-02-27 13:04:27 +00:00

Branches

586fa033a6 · design: ensure all_modules outlives pass when building WITH_PYTHON · Updated 2025-05-10 15:19:51 +00:00

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068dd77a14 · check: fix up tests · Updated 2025-05-08 13:30:49 +00:00

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68c11321c0 · remove invalid tests · Updated 2025-05-07 15:52:31 +00:00

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11c846de5c · aiger, xaiger, aiger2: add -no_version · Updated 2025-04-30 17:51:35 +00:00

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ff2a8af545 · quicklogic: workaround for #5069 · Updated 2025-04-28 14:01:12 +00:00

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f0545d5bc1 · simplify: fix another struct wiretype attr memory leak · Updated 2025-04-28 11:18:00 +00:00

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532f9abc72 · opt_clean: hide it behind -x · Updated 2025-04-23 20:41:04 +00:00

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54ea41c40c · Add test to verify that the liberty format is properly parsed. · Updated 2025-04-23 19:41:13 +00:00

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f2d7833b2b · test-compile: gcc-14 as newest · Updated 2025-03-27 21:31:06 +00:00

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aa4d59cdcb · Trigger abc segfault for testing · Updated 2025-03-26 11:20:57 +00:00

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95be73467d · opt_expr: chop up the kitchen sink · Updated 2025-03-20 14:58:39 +00:00

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1646bcd474 · WIP · Updated 2025-03-19 17:19:07 +00:00

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2e31dd3070 · quicklogic: add fracturable full-block dspv1 to keep vendor simulation model unchanged · Updated 2025-03-10 16:12:31 +00:00

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913ac04764 · hierarchy: Derive abstract cells in top mod · Updated 2025-03-06 21:12:29 +00:00

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5eb46f95c2 · equiv_induct: change missing SAT model warning to error · Updated 2025-03-06 17:15:52 +00:00

1950
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caf921161c · quicklogic: ql_dsp_io_regs debug print · Updated 2025-03-06 17:01:28 +00:00

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e6d7c033e5 · ql_dsp_macc: whitespace. NFC · Updated 2025-02-27 16:37:18 +00:00    mirrors

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d2040a9506 · synth_quicklogic: enable dspv2 tests, fix -dspv2 · Updated 2025-02-25 10:59:41 +00:00    mirrors

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c87bf56efb · CMake: more generated files · Updated 2025-02-14 10:12:33 +00:00    mirrors

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43b5e109f3 · formalff: Document -declockgate option · Updated 2025-02-12 16:45:02 +00:00    mirrors

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