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quicklogic: workaround for #5069

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This commit is contained in:
Emil J. Tywoniak 2025-04-28 16:01:12 +02:00
parent ab614b1271
commit ff2a8af545
2 changed files with 8 additions and 46 deletions
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27
techlibs/quicklogic/qlf_k6n10f/brams_map.v
View file

@ -361,12 +361,7 @@ output wire [RD_DATA_WIDTH-1 :0] RDATA_o;
.RD1_ADDR_WIDTH(RD_ADDR_WIDTH),
.WR1_DATA_WIDTH(WR_DATA_WIDTH),
.RD1_DATA_WIDTH(RD_DATA_WIDTH),
.BE1_WIDTH(BE_WIDTH),
.WR2_ADDR_WIDTH(),
.RD2_ADDR_WIDTH(),
.WR2_DATA_WIDTH(),
.RD2_DATA_WIDTH(),
.BE2_WIDTH()
.BE1_WIDTH(BE_WIDTH)
) U1
(
.RESET_ni(1'b1),
@ -1240,13 +1235,7 @@ BRAM2x18_dP #(
.PORT_A1_WR_BE_WIDTH(PORT_A_WR_BE_WIDTH),
.PORT_B1_AWIDTH(PORT_B_AWIDTH),
.PORT_B1_DWIDTH(PORT_B_DWIDTH),
.PORT_B1_WR_BE_WIDTH(PORT_B_WR_BE_WIDTH),
.PORT_A2_AWIDTH(),
.PORT_A2_DWIDTH(),
.PORT_A2_WR_BE_WIDTH(),
.PORT_B2_AWIDTH(),
.PORT_B2_DWIDTH(),
.PORT_B2_WR_BE_WIDTH()
.PORT_B1_WR_BE_WIDTH(PORT_B_WR_BE_WIDTH)
) U1 (
.PORT_A1_CLK_i(PORT_A_CLK_i),
.PORT_A1_WEN_i(PORT_A_WEN_i),
@ -2233,11 +2222,7 @@ module SFIFO_18K_BLK (
.WR1_DATA_WIDTH(WR_DATA_WIDTH),
.RD1_DATA_WIDTH(RD_DATA_WIDTH),
.UPAE_DBITS1(UPAE_DBITS),
.UPAF_DBITS1(UPAF_DBITS),
.WR2_DATA_WIDTH(),
.RD2_DATA_WIDTH(),
.UPAE_DBITS2(),
.UPAF_DBITS2()
.UPAF_DBITS1(UPAF_DBITS)
) U1
(
.DIN1(DIN),
@ -2554,11 +2539,7 @@ module AFIFO_18K_BLK (
.WR1_DATA_WIDTH(WR_DATA_WIDTH),
.RD1_DATA_WIDTH(RD_DATA_WIDTH),
.UPAE_DBITS1(UPAE_DBITS),
.UPAF_DBITS1(UPAF_DBITS),
.WR2_DATA_WIDTH(),
.RD2_DATA_WIDTH(),
.UPAE_DBITS2(),
.UPAF_DBITS2()
.UPAF_DBITS1(UPAF_DBITS)
) U1
(
.DIN1(DIN),

27
techlibs/quicklogic/qlf_k6n10f/brams_sim.v
View file

@ -1400,12 +1400,7 @@ output wire [RD_DATA_WIDTH-1 :0] RDATA_o;
.RD1_ADDR_WIDTH(RD_ADDR_WIDTH),
.WR1_DATA_WIDTH(WR_DATA_WIDTH),
.RD1_DATA_WIDTH(RD_DATA_WIDTH),
.BE1_WIDTH(BE_WIDTH),
.WR2_ADDR_WIDTH(),
.RD2_ADDR_WIDTH(),
.WR2_DATA_WIDTH(),
.RD2_DATA_WIDTH(),
.BE2_WIDTH()
.BE1_WIDTH(BE_WIDTH)
) U1
(
.RESET_ni(1'b1),
@ -2819,13 +2814,7 @@ BRAM2x18_dP #(
.PORT_A1_WR_BE_WIDTH(PORT_A_WR_BE_WIDTH),
.PORT_B1_AWIDTH(PORT_B_AWIDTH),
.PORT_B1_DWIDTH(PORT_B_DWIDTH),
.PORT_B1_WR_BE_WIDTH(PORT_B_WR_BE_WIDTH),
.PORT_A2_AWIDTH(),
.PORT_A2_DWIDTH(),
.PORT_A2_WR_BE_WIDTH(),
.PORT_B2_AWIDTH(),
.PORT_B2_DWIDTH(),
.PORT_B2_WR_BE_WIDTH()
.PORT_B1_WR_BE_WIDTH(PORT_B_WR_BE_WIDTH)
) U1 (
.PORT_A1_CLK_i(PORT_A_CLK_i),
.PORT_A1_WEN_i(PORT_A_WEN_i),
@ -3470,11 +3459,7 @@ module SFIFO_18K_BLK (
.WR1_DATA_WIDTH(WR_DATA_WIDTH),
.RD1_DATA_WIDTH(RD_DATA_WIDTH),
.UPAE_DBITS1(UPAE_DBITS),
.UPAF_DBITS1(UPAF_DBITS),
.WR2_DATA_WIDTH(),
.RD2_DATA_WIDTH(),
.UPAE_DBITS2(),
.UPAF_DBITS2()
.UPAF_DBITS1(UPAF_DBITS)
) U1
(
.DIN1(DIN),
@ -3995,11 +3980,7 @@ module AFIFO_18K_BLK (
.WR1_DATA_WIDTH(WR_DATA_WIDTH),
.RD1_DATA_WIDTH(RD_DATA_WIDTH),
.UPAE_DBITS1(UPAE_DBITS),
.UPAF_DBITS1(UPAF_DBITS),
.WR2_DATA_WIDTH(),
.RD2_DATA_WIDTH(),
.UPAE_DBITS2(),
.UPAF_DBITS2()
.UPAF_DBITS1(UPAF_DBITS)
) U1
(
.DIN1(DIN),