firrtl: don't generate as many duplicate wires when compiling expressions
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SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
2 changed files with 652 additions and 601 deletions
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@ -808,40 +808,8 @@ circuit check_enum_cmp_eq:
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connect _cast_bits_to_array_expr_flattened_1[2], bits(bits(rhs.body, 2, 0), 2, 2)
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connect _cast_bits_to_array_expr_1[2], _cast_bits_to_array_expr_flattened_1[2]
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connect _array_literal_expr[0], eq(_cast_bits_to_array_expr[0], _cast_bits_to_array_expr_1[0])
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wire _cast_bits_to_array_expr_2: UInt<1>[3]
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wire _cast_bits_to_array_expr_flattened_2: UInt<1>[3]
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connect _cast_bits_to_array_expr_flattened_2[0], bits(bits(lhs.body, 2, 0), 0, 0)
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connect _cast_bits_to_array_expr_2[0], _cast_bits_to_array_expr_flattened_2[0]
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connect _cast_bits_to_array_expr_flattened_2[1], bits(bits(lhs.body, 2, 0), 1, 1)
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connect _cast_bits_to_array_expr_2[1], _cast_bits_to_array_expr_flattened_2[1]
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connect _cast_bits_to_array_expr_flattened_2[2], bits(bits(lhs.body, 2, 0), 2, 2)
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connect _cast_bits_to_array_expr_2[2], _cast_bits_to_array_expr_flattened_2[2]
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wire _cast_bits_to_array_expr_3: UInt<1>[3]
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wire _cast_bits_to_array_expr_flattened_3: UInt<1>[3]
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connect _cast_bits_to_array_expr_flattened_3[0], bits(bits(rhs.body, 2, 0), 0, 0)
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connect _cast_bits_to_array_expr_3[0], _cast_bits_to_array_expr_flattened_3[0]
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connect _cast_bits_to_array_expr_flattened_3[1], bits(bits(rhs.body, 2, 0), 1, 1)
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connect _cast_bits_to_array_expr_3[1], _cast_bits_to_array_expr_flattened_3[1]
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connect _cast_bits_to_array_expr_flattened_3[2], bits(bits(rhs.body, 2, 0), 2, 2)
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connect _cast_bits_to_array_expr_3[2], _cast_bits_to_array_expr_flattened_3[2]
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connect _array_literal_expr[1], eq(_cast_bits_to_array_expr_2[1], _cast_bits_to_array_expr_3[1])
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wire _cast_bits_to_array_expr_4: UInt<1>[3]
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wire _cast_bits_to_array_expr_flattened_4: UInt<1>[3]
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connect _cast_bits_to_array_expr_flattened_4[0], bits(bits(lhs.body, 2, 0), 0, 0)
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connect _cast_bits_to_array_expr_4[0], _cast_bits_to_array_expr_flattened_4[0]
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connect _cast_bits_to_array_expr_flattened_4[1], bits(bits(lhs.body, 2, 0), 1, 1)
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connect _cast_bits_to_array_expr_4[1], _cast_bits_to_array_expr_flattened_4[1]
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connect _cast_bits_to_array_expr_flattened_4[2], bits(bits(lhs.body, 2, 0), 2, 2)
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connect _cast_bits_to_array_expr_4[2], _cast_bits_to_array_expr_flattened_4[2]
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wire _cast_bits_to_array_expr_5: UInt<1>[3]
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wire _cast_bits_to_array_expr_flattened_5: UInt<1>[3]
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connect _cast_bits_to_array_expr_flattened_5[0], bits(bits(rhs.body, 2, 0), 0, 0)
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connect _cast_bits_to_array_expr_5[0], _cast_bits_to_array_expr_flattened_5[0]
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connect _cast_bits_to_array_expr_flattened_5[1], bits(bits(rhs.body, 2, 0), 1, 1)
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connect _cast_bits_to_array_expr_5[1], _cast_bits_to_array_expr_flattened_5[1]
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connect _cast_bits_to_array_expr_flattened_5[2], bits(bits(rhs.body, 2, 0), 2, 2)
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connect _cast_bits_to_array_expr_5[2], _cast_bits_to_array_expr_flattened_5[2]
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connect _array_literal_expr[2], eq(_cast_bits_to_array_expr_4[2], _cast_bits_to_array_expr_5[2])
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connect _array_literal_expr[1], eq(_cast_bits_to_array_expr[1], _cast_bits_to_array_expr_1[1])
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connect _array_literal_expr[2], eq(_cast_bits_to_array_expr[2], _cast_bits_to_array_expr_1[2])
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wire _cast_array_to_bits_expr: UInt<1>[3]
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connect _cast_array_to_bits_expr[0], _array_literal_expr[0]
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connect _cast_array_to_bits_expr[1], _array_literal_expr[1]
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@ -901,40 +869,8 @@ circuit check_enum_cmp_eq:
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connect _cast_bits_to_array_expr_flattened_1[2], bits(bits(rhs.body, 2, 0), 2, 2)
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connect _cast_bits_to_array_expr_1[2], _cast_bits_to_array_expr_flattened_1[2]
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connect _array_literal_expr[0], eq(_cast_bits_to_array_expr[0], _cast_bits_to_array_expr_1[0])
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wire _cast_bits_to_array_expr_2: UInt<1>[3]
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wire _cast_bits_to_array_expr_flattened_2: UInt<1>[3]
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connect _cast_bits_to_array_expr_flattened_2[0], bits(bits(lhs.body, 2, 0), 0, 0)
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connect _cast_bits_to_array_expr_2[0], _cast_bits_to_array_expr_flattened_2[0]
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connect _cast_bits_to_array_expr_flattened_2[1], bits(bits(lhs.body, 2, 0), 1, 1)
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connect _cast_bits_to_array_expr_2[1], _cast_bits_to_array_expr_flattened_2[1]
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connect _cast_bits_to_array_expr_flattened_2[2], bits(bits(lhs.body, 2, 0), 2, 2)
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connect _cast_bits_to_array_expr_2[2], _cast_bits_to_array_expr_flattened_2[2]
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wire _cast_bits_to_array_expr_3: UInt<1>[3]
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wire _cast_bits_to_array_expr_flattened_3: UInt<1>[3]
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connect _cast_bits_to_array_expr_flattened_3[0], bits(bits(rhs.body, 2, 0), 0, 0)
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connect _cast_bits_to_array_expr_3[0], _cast_bits_to_array_expr_flattened_3[0]
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connect _cast_bits_to_array_expr_flattened_3[1], bits(bits(rhs.body, 2, 0), 1, 1)
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connect _cast_bits_to_array_expr_3[1], _cast_bits_to_array_expr_flattened_3[1]
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connect _cast_bits_to_array_expr_flattened_3[2], bits(bits(rhs.body, 2, 0), 2, 2)
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connect _cast_bits_to_array_expr_3[2], _cast_bits_to_array_expr_flattened_3[2]
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connect _array_literal_expr[1], eq(_cast_bits_to_array_expr_2[1], _cast_bits_to_array_expr_3[1])
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wire _cast_bits_to_array_expr_4: UInt<1>[3]
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wire _cast_bits_to_array_expr_flattened_4: UInt<1>[3]
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connect _cast_bits_to_array_expr_flattened_4[0], bits(bits(lhs.body, 2, 0), 0, 0)
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connect _cast_bits_to_array_expr_4[0], _cast_bits_to_array_expr_flattened_4[0]
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connect _cast_bits_to_array_expr_flattened_4[1], bits(bits(lhs.body, 2, 0), 1, 1)
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connect _cast_bits_to_array_expr_4[1], _cast_bits_to_array_expr_flattened_4[1]
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connect _cast_bits_to_array_expr_flattened_4[2], bits(bits(lhs.body, 2, 0), 2, 2)
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connect _cast_bits_to_array_expr_4[2], _cast_bits_to_array_expr_flattened_4[2]
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wire _cast_bits_to_array_expr_5: UInt<1>[3]
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wire _cast_bits_to_array_expr_flattened_5: UInt<1>[3]
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connect _cast_bits_to_array_expr_flattened_5[0], bits(bits(rhs.body, 2, 0), 0, 0)
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connect _cast_bits_to_array_expr_5[0], _cast_bits_to_array_expr_flattened_5[0]
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connect _cast_bits_to_array_expr_flattened_5[1], bits(bits(rhs.body, 2, 0), 1, 1)
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connect _cast_bits_to_array_expr_5[1], _cast_bits_to_array_expr_flattened_5[1]
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connect _cast_bits_to_array_expr_flattened_5[2], bits(bits(rhs.body, 2, 0), 2, 2)
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connect _cast_bits_to_array_expr_5[2], _cast_bits_to_array_expr_flattened_5[2]
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connect _array_literal_expr[2], eq(_cast_bits_to_array_expr_4[2], _cast_bits_to_array_expr_5[2])
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connect _array_literal_expr[1], eq(_cast_bits_to_array_expr[1], _cast_bits_to_array_expr_1[1])
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connect _array_literal_expr[2], eq(_cast_bits_to_array_expr[2], _cast_bits_to_array_expr_1[2])
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wire _cast_array_to_bits_expr: UInt<1>[3]
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connect _cast_array_to_bits_expr[0], _array_literal_expr[0]
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connect _cast_array_to_bits_expr[1], _array_literal_expr[1]
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@ -993,40 +929,8 @@ circuit check_enum_cmp_eq:
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connect _cast_bits_to_array_expr_flattened_1[2], bits(bits(bits(rhs, 9, 2), 2, 0), 2, 2)
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connect _cast_bits_to_array_expr_1[2], _cast_bits_to_array_expr_flattened_1[2]
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connect _array_literal_expr[0], eq(_cast_bits_to_array_expr[0], _cast_bits_to_array_expr_1[0])
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wire _cast_bits_to_array_expr_2: UInt<1>[3]
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wire _cast_bits_to_array_expr_flattened_2: UInt<1>[3]
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connect _cast_bits_to_array_expr_flattened_2[0], bits(bits(bits(lhs, 9, 2), 2, 0), 0, 0)
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connect _cast_bits_to_array_expr_2[0], _cast_bits_to_array_expr_flattened_2[0]
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connect _cast_bits_to_array_expr_flattened_2[1], bits(bits(bits(lhs, 9, 2), 2, 0), 1, 1)
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connect _cast_bits_to_array_expr_2[1], _cast_bits_to_array_expr_flattened_2[1]
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connect _cast_bits_to_array_expr_flattened_2[2], bits(bits(bits(lhs, 9, 2), 2, 0), 2, 2)
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connect _cast_bits_to_array_expr_2[2], _cast_bits_to_array_expr_flattened_2[2]
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wire _cast_bits_to_array_expr_3: UInt<1>[3]
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wire _cast_bits_to_array_expr_flattened_3: UInt<1>[3]
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connect _cast_bits_to_array_expr_flattened_3[0], bits(bits(bits(rhs, 9, 2), 2, 0), 0, 0)
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connect _cast_bits_to_array_expr_3[0], _cast_bits_to_array_expr_flattened_3[0]
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connect _cast_bits_to_array_expr_flattened_3[1], bits(bits(bits(rhs, 9, 2), 2, 0), 1, 1)
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connect _cast_bits_to_array_expr_3[1], _cast_bits_to_array_expr_flattened_3[1]
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connect _cast_bits_to_array_expr_flattened_3[2], bits(bits(bits(rhs, 9, 2), 2, 0), 2, 2)
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connect _cast_bits_to_array_expr_3[2], _cast_bits_to_array_expr_flattened_3[2]
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connect _array_literal_expr[1], eq(_cast_bits_to_array_expr_2[1], _cast_bits_to_array_expr_3[1])
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wire _cast_bits_to_array_expr_4: UInt<1>[3]
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wire _cast_bits_to_array_expr_flattened_4: UInt<1>[3]
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connect _cast_bits_to_array_expr_flattened_4[0], bits(bits(bits(lhs, 9, 2), 2, 0), 0, 0)
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connect _cast_bits_to_array_expr_4[0], _cast_bits_to_array_expr_flattened_4[0]
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connect _cast_bits_to_array_expr_flattened_4[1], bits(bits(bits(lhs, 9, 2), 2, 0), 1, 1)
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connect _cast_bits_to_array_expr_4[1], _cast_bits_to_array_expr_flattened_4[1]
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connect _cast_bits_to_array_expr_flattened_4[2], bits(bits(bits(lhs, 9, 2), 2, 0), 2, 2)
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connect _cast_bits_to_array_expr_4[2], _cast_bits_to_array_expr_flattened_4[2]
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wire _cast_bits_to_array_expr_5: UInt<1>[3]
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wire _cast_bits_to_array_expr_flattened_5: UInt<1>[3]
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connect _cast_bits_to_array_expr_flattened_5[0], bits(bits(bits(rhs, 9, 2), 2, 0), 0, 0)
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connect _cast_bits_to_array_expr_5[0], _cast_bits_to_array_expr_flattened_5[0]
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connect _cast_bits_to_array_expr_flattened_5[1], bits(bits(bits(rhs, 9, 2), 2, 0), 1, 1)
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connect _cast_bits_to_array_expr_5[1], _cast_bits_to_array_expr_flattened_5[1]
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connect _cast_bits_to_array_expr_flattened_5[2], bits(bits(bits(rhs, 9, 2), 2, 0), 2, 2)
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connect _cast_bits_to_array_expr_5[2], _cast_bits_to_array_expr_flattened_5[2]
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connect _array_literal_expr[2], eq(_cast_bits_to_array_expr_4[2], _cast_bits_to_array_expr_5[2])
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connect _array_literal_expr[1], eq(_cast_bits_to_array_expr[1], _cast_bits_to_array_expr_1[1])
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connect _array_literal_expr[2], eq(_cast_bits_to_array_expr[2], _cast_bits_to_array_expr_1[2])
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wire _cast_array_to_bits_expr: UInt<1>[3]
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connect _cast_array_to_bits_expr[0], _array_literal_expr[0]
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connect _cast_array_to_bits_expr[1], _array_literal_expr[1]
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@ -3925,21 +3829,10 @@ circuit check_enum_connect_any:
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connect __connect_variant_body_1, _bundle_literal_expr_1 @[module-XXXXXXXXXX.rs 8:1]
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HdlSome:
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wire __connect_variant_body_2: SInt<1> @[module-XXXXXXXXXX.rs 8:1]
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wire _cast_bits_to_bundle_expr_1: Ty5
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wire _cast_bits_to_bundle_expr_flattened_1: Ty6
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connect _cast_bits_to_bundle_expr_flattened_1.tag, bits(bits(i2.body, 2, 0), 0, 0)
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wire _cast_bits_to_enum_expr_1: Ty3
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when eq(UInt<1>(0), tail(_cast_bits_to_bundle_expr_flattened_1.tag, 0)):
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connect _cast_bits_to_enum_expr_1, {|HdlNone, HdlSome|}(HdlNone)
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else:
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connect _cast_bits_to_enum_expr_1, {|HdlNone, HdlSome|}(HdlSome)
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connect _cast_bits_to_bundle_expr_1.tag, _cast_bits_to_enum_expr_1
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connect _cast_bits_to_bundle_expr_flattened_1.body, bits(bits(i2.body, 2, 0), 2, 1)
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connect _cast_bits_to_bundle_expr_1.body, _cast_bits_to_bundle_expr_flattened_1.body
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; connect different types:
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; lhs: SInt<1>
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; rhs: SInt<2>
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connect __connect_variant_body_2, asSInt(bits(_cast_bits_to_bundle_expr_1.body, 1, 0)) @[module-XXXXXXXXXX.rs 8:1]
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connect __connect_variant_body_2, asSInt(bits(_cast_bits_to_bundle_expr.body, 1, 0)) @[module-XXXXXXXXXX.rs 8:1]
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wire _bundle_literal_expr_2: Ty4
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connect _bundle_literal_expr_2.tag, {|HdlNone, HdlSome|}(HdlSome)
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connect _bundle_literal_expr_2.body, asUInt(__connect_variant_body_2)
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@ -3961,18 +3854,18 @@ circuit check_enum_connect_any:
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connect o1, _bundle_literal_expr_3 @[module-XXXXXXXXXX.rs 8:1]
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C:
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wire __connect_variant_body_3: Ty8 @[module-XXXXXXXXXX.rs 8:1]
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wire _cast_bits_to_bundle_expr_2: Ty8
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wire _cast_bits_to_bundle_expr_flattened_2: Ty9
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connect _cast_bits_to_bundle_expr_flattened_2.tag, bits(bits(i2.body, 0, 0), 0, 0)
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wire _cast_bits_to_enum_expr_2: Ty3
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when eq(UInt<1>(0), tail(_cast_bits_to_bundle_expr_flattened_2.tag, 0)):
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connect _cast_bits_to_enum_expr_2, {|HdlNone, HdlSome|}(HdlNone)
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wire _cast_bits_to_bundle_expr_1: Ty8
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wire _cast_bits_to_bundle_expr_flattened_1: Ty9
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connect _cast_bits_to_bundle_expr_flattened_1.tag, bits(bits(i2.body, 0, 0), 0, 0)
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wire _cast_bits_to_enum_expr_1: Ty3
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when eq(UInt<1>(0), tail(_cast_bits_to_bundle_expr_flattened_1.tag, 0)):
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connect _cast_bits_to_enum_expr_1, {|HdlNone, HdlSome|}(HdlNone)
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else:
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connect _cast_bits_to_enum_expr_2, {|HdlNone, HdlSome|}(HdlSome)
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connect _cast_bits_to_bundle_expr_2.tag, _cast_bits_to_enum_expr_2
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connect _cast_bits_to_bundle_expr_flattened_2.body, UInt<0>(0)
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connect _cast_bits_to_bundle_expr_2.body, _cast_bits_to_bundle_expr_flattened_2.body
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connect __connect_variant_body_3, _cast_bits_to_bundle_expr_2 @[module-XXXXXXXXXX.rs 8:1]
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connect _cast_bits_to_enum_expr_1, {|HdlNone, HdlSome|}(HdlSome)
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connect _cast_bits_to_bundle_expr_1.tag, _cast_bits_to_enum_expr_1
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connect _cast_bits_to_bundle_expr_flattened_1.body, UInt<0>(0)
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connect _cast_bits_to_bundle_expr_1.body, _cast_bits_to_bundle_expr_flattened_1.body
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connect __connect_variant_body_3, _cast_bits_to_bundle_expr_1 @[module-XXXXXXXXXX.rs 8:1]
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wire _bundle_literal_expr_4: Ty1
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connect _bundle_literal_expr_4.tag, {|A, B, C|}(C)
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wire _cast_bundle_to_bits_expr_1: Ty9
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@ -4001,18 +3894,18 @@ circuit check_enum_connect_any:
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connect o2, _bundle_literal_expr_5 @[module-XXXXXXXXXX.rs 9:1]
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B:
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wire __connect_variant_body_5: Ty5 @[module-XXXXXXXXXX.rs 9:1]
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wire _cast_bits_to_bundle_expr_3: Ty4
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wire _cast_bits_to_bundle_expr_flattened_3: Ty7
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connect _cast_bits_to_bundle_expr_flattened_3.tag, bits(bits(i1.body, 1, 0), 0, 0)
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wire _cast_bits_to_enum_expr_3: Ty3
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when eq(UInt<1>(0), tail(_cast_bits_to_bundle_expr_flattened_3.tag, 0)):
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connect _cast_bits_to_enum_expr_3, {|HdlNone, HdlSome|}(HdlNone)
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wire _cast_bits_to_bundle_expr_2: Ty4
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wire _cast_bits_to_bundle_expr_flattened_2: Ty7
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connect _cast_bits_to_bundle_expr_flattened_2.tag, bits(bits(i1.body, 1, 0), 0, 0)
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wire _cast_bits_to_enum_expr_2: Ty3
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when eq(UInt<1>(0), tail(_cast_bits_to_bundle_expr_flattened_2.tag, 0)):
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connect _cast_bits_to_enum_expr_2, {|HdlNone, HdlSome|}(HdlNone)
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else:
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connect _cast_bits_to_enum_expr_3, {|HdlNone, HdlSome|}(HdlSome)
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connect _cast_bits_to_bundle_expr_3.tag, _cast_bits_to_enum_expr_3
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connect _cast_bits_to_bundle_expr_flattened_3.body, bits(bits(i1.body, 1, 0), 1, 1)
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connect _cast_bits_to_bundle_expr_3.body, _cast_bits_to_bundle_expr_flattened_3.body
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match _cast_bits_to_bundle_expr_3.tag: @[module-XXXXXXXXXX.rs 9:1]
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connect _cast_bits_to_enum_expr_2, {|HdlNone, HdlSome|}(HdlSome)
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connect _cast_bits_to_bundle_expr_2.tag, _cast_bits_to_enum_expr_2
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connect _cast_bits_to_bundle_expr_flattened_2.body, bits(bits(i1.body, 1, 0), 1, 1)
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connect _cast_bits_to_bundle_expr_2.body, _cast_bits_to_bundle_expr_flattened_2.body
|
||||
match _cast_bits_to_bundle_expr_2.tag: @[module-XXXXXXXXXX.rs 9:1]
|
||||
HdlNone:
|
||||
wire _bundle_literal_expr_6: Ty5
|
||||
connect _bundle_literal_expr_6.tag, {|HdlNone, HdlSome|}(HdlNone)
|
||||
|
|
@ -4020,21 +3913,10 @@ circuit check_enum_connect_any:
|
|||
connect __connect_variant_body_5, _bundle_literal_expr_6 @[module-XXXXXXXXXX.rs 9:1]
|
||||
HdlSome:
|
||||
wire __connect_variant_body_6: SInt<2> @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire _cast_bits_to_bundle_expr_4: Ty4
|
||||
wire _cast_bits_to_bundle_expr_flattened_4: Ty7
|
||||
connect _cast_bits_to_bundle_expr_flattened_4.tag, bits(bits(i1.body, 1, 0), 0, 0)
|
||||
wire _cast_bits_to_enum_expr_4: Ty3
|
||||
when eq(UInt<1>(0), tail(_cast_bits_to_bundle_expr_flattened_4.tag, 0)):
|
||||
connect _cast_bits_to_enum_expr_4, {|HdlNone, HdlSome|}(HdlNone)
|
||||
else:
|
||||
connect _cast_bits_to_enum_expr_4, {|HdlNone, HdlSome|}(HdlSome)
|
||||
connect _cast_bits_to_bundle_expr_4.tag, _cast_bits_to_enum_expr_4
|
||||
connect _cast_bits_to_bundle_expr_flattened_4.body, bits(bits(i1.body, 1, 0), 1, 1)
|
||||
connect _cast_bits_to_bundle_expr_4.body, _cast_bits_to_bundle_expr_flattened_4.body
|
||||
; connect different types:
|
||||
; lhs: SInt<2>
|
||||
; rhs: SInt<1>
|
||||
connect __connect_variant_body_6, asSInt(bits(_cast_bits_to_bundle_expr_4.body, 0, 0)) @[module-XXXXXXXXXX.rs 9:1]
|
||||
connect __connect_variant_body_6, asSInt(bits(_cast_bits_to_bundle_expr_2.body, 0, 0)) @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire _bundle_literal_expr_7: Ty5
|
||||
connect _bundle_literal_expr_7.tag, {|HdlNone, HdlSome|}(HdlSome)
|
||||
connect _bundle_literal_expr_7.body, asUInt(__connect_variant_body_6)
|
||||
|
|
@ -4056,18 +3938,18 @@ circuit check_enum_connect_any:
|
|||
connect o2, _bundle_literal_expr_8 @[module-XXXXXXXXXX.rs 9:1]
|
||||
C:
|
||||
wire __connect_variant_body_7: Ty8 @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire _cast_bits_to_bundle_expr_5: Ty8
|
||||
wire _cast_bits_to_bundle_expr_flattened_5: Ty9
|
||||
connect _cast_bits_to_bundle_expr_flattened_5.tag, bits(bits(i1.body, 0, 0), 0, 0)
|
||||
wire _cast_bits_to_enum_expr_5: Ty3
|
||||
when eq(UInt<1>(0), tail(_cast_bits_to_bundle_expr_flattened_5.tag, 0)):
|
||||
connect _cast_bits_to_enum_expr_5, {|HdlNone, HdlSome|}(HdlNone)
|
||||
wire _cast_bits_to_bundle_expr_3: Ty8
|
||||
wire _cast_bits_to_bundle_expr_flattened_3: Ty9
|
||||
connect _cast_bits_to_bundle_expr_flattened_3.tag, bits(bits(i1.body, 0, 0), 0, 0)
|
||||
wire _cast_bits_to_enum_expr_3: Ty3
|
||||
when eq(UInt<1>(0), tail(_cast_bits_to_bundle_expr_flattened_3.tag, 0)):
|
||||
connect _cast_bits_to_enum_expr_3, {|HdlNone, HdlSome|}(HdlNone)
|
||||
else:
|
||||
connect _cast_bits_to_enum_expr_5, {|HdlNone, HdlSome|}(HdlSome)
|
||||
connect _cast_bits_to_bundle_expr_5.tag, _cast_bits_to_enum_expr_5
|
||||
connect _cast_bits_to_bundle_expr_flattened_5.body, UInt<0>(0)
|
||||
connect _cast_bits_to_bundle_expr_5.body, _cast_bits_to_bundle_expr_flattened_5.body
|
||||
connect __connect_variant_body_7, _cast_bits_to_bundle_expr_5 @[module-XXXXXXXXXX.rs 9:1]
|
||||
connect _cast_bits_to_enum_expr_3, {|HdlNone, HdlSome|}(HdlSome)
|
||||
connect _cast_bits_to_bundle_expr_3.tag, _cast_bits_to_enum_expr_3
|
||||
connect _cast_bits_to_bundle_expr_flattened_3.body, UInt<0>(0)
|
||||
connect _cast_bits_to_bundle_expr_3.body, _cast_bits_to_bundle_expr_flattened_3.body
|
||||
connect __connect_variant_body_7, _cast_bits_to_bundle_expr_3 @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire _bundle_literal_expr_9: Ty2
|
||||
connect _bundle_literal_expr_9.tag, {|A, B, C|}(C)
|
||||
wire _cast_bundle_to_bits_expr_3: Ty9
|
||||
|
|
@ -4134,16 +4016,10 @@ circuit check_enum_connect_any:
|
|||
connect __connect_variant_body_1, _bundle_literal_expr_1 @[module-XXXXXXXXXX.rs 8:1]
|
||||
else:
|
||||
wire __connect_variant_body_2: SInt<1> @[module-XXXXXXXXXX.rs 8:1]
|
||||
wire _cast_bits_to_bundle_expr_1: Ty3
|
||||
wire _cast_bits_to_bundle_expr_flattened_1: Ty3
|
||||
connect _cast_bits_to_bundle_expr_flattened_1.tag, bits(bits(i2.body, 2, 0), 0, 0)
|
||||
connect _cast_bits_to_bundle_expr_1.tag, _cast_bits_to_bundle_expr_flattened_1.tag
|
||||
connect _cast_bits_to_bundle_expr_flattened_1.body, bits(bits(i2.body, 2, 0), 2, 1)
|
||||
connect _cast_bits_to_bundle_expr_1.body, _cast_bits_to_bundle_expr_flattened_1.body
|
||||
; connect different types:
|
||||
; lhs: SInt<1>
|
||||
; rhs: SInt<2>
|
||||
connect __connect_variant_body_2, asSInt(bits(_cast_bits_to_bundle_expr_1.body, 1, 0)) @[module-XXXXXXXXXX.rs 8:1]
|
||||
connect __connect_variant_body_2, asSInt(bits(_cast_bits_to_bundle_expr.body, 1, 0)) @[module-XXXXXXXXXX.rs 8:1]
|
||||
wire _bundle_literal_expr_2: Ty2
|
||||
connect _bundle_literal_expr_2.tag, UInt<1>(0h1)
|
||||
connect _bundle_literal_expr_2.body, asUInt(__connect_variant_body_2)
|
||||
|
|
@ -4159,13 +4035,13 @@ circuit check_enum_connect_any:
|
|||
connect o1, _bundle_literal_expr_3 @[module-XXXXXXXXXX.rs 8:1]
|
||||
else:
|
||||
wire __connect_variant_body_3: Ty4 @[module-XXXXXXXXXX.rs 8:1]
|
||||
wire _cast_bits_to_bundle_expr_2: Ty4
|
||||
wire _cast_bits_to_bundle_expr_flattened_2: Ty4
|
||||
connect _cast_bits_to_bundle_expr_flattened_2.tag, bits(bits(i2.body, 0, 0), 0, 0)
|
||||
connect _cast_bits_to_bundle_expr_2.tag, _cast_bits_to_bundle_expr_flattened_2.tag
|
||||
connect _cast_bits_to_bundle_expr_flattened_2.body, UInt<0>(0)
|
||||
connect _cast_bits_to_bundle_expr_2.body, _cast_bits_to_bundle_expr_flattened_2.body
|
||||
connect __connect_variant_body_3, _cast_bits_to_bundle_expr_2 @[module-XXXXXXXXXX.rs 8:1]
|
||||
wire _cast_bits_to_bundle_expr_1: Ty4
|
||||
wire _cast_bits_to_bundle_expr_flattened_1: Ty4
|
||||
connect _cast_bits_to_bundle_expr_flattened_1.tag, bits(bits(i2.body, 0, 0), 0, 0)
|
||||
connect _cast_bits_to_bundle_expr_1.tag, _cast_bits_to_bundle_expr_flattened_1.tag
|
||||
connect _cast_bits_to_bundle_expr_flattened_1.body, UInt<0>(0)
|
||||
connect _cast_bits_to_bundle_expr_1.body, _cast_bits_to_bundle_expr_flattened_1.body
|
||||
connect __connect_variant_body_3, _cast_bits_to_bundle_expr_1 @[module-XXXXXXXXXX.rs 8:1]
|
||||
wire _bundle_literal_expr_4: Ty0
|
||||
connect _bundle_literal_expr_4.tag, UInt<2>(0h2)
|
||||
wire _cast_bundle_to_bits_expr_1: Ty4
|
||||
|
|
@ -4187,29 +4063,23 @@ circuit check_enum_connect_any:
|
|||
connect o2, _bundle_literal_expr_5 @[module-XXXXXXXXXX.rs 9:1]
|
||||
else when eq(i1.tag, UInt<2>(0h1)): @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire __connect_variant_body_5: Ty3 @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire _cast_bits_to_bundle_expr_3: Ty2
|
||||
wire _cast_bits_to_bundle_expr_flattened_3: Ty2
|
||||
connect _cast_bits_to_bundle_expr_flattened_3.tag, bits(bits(i1.body, 1, 0), 0, 0)
|
||||
connect _cast_bits_to_bundle_expr_3.tag, _cast_bits_to_bundle_expr_flattened_3.tag
|
||||
connect _cast_bits_to_bundle_expr_flattened_3.body, bits(bits(i1.body, 1, 0), 1, 1)
|
||||
connect _cast_bits_to_bundle_expr_3.body, _cast_bits_to_bundle_expr_flattened_3.body
|
||||
when eq(_cast_bits_to_bundle_expr_3.tag, UInt<1>(0h0)): @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire _cast_bits_to_bundle_expr_2: Ty2
|
||||
wire _cast_bits_to_bundle_expr_flattened_2: Ty2
|
||||
connect _cast_bits_to_bundle_expr_flattened_2.tag, bits(bits(i1.body, 1, 0), 0, 0)
|
||||
connect _cast_bits_to_bundle_expr_2.tag, _cast_bits_to_bundle_expr_flattened_2.tag
|
||||
connect _cast_bits_to_bundle_expr_flattened_2.body, bits(bits(i1.body, 1, 0), 1, 1)
|
||||
connect _cast_bits_to_bundle_expr_2.body, _cast_bits_to_bundle_expr_flattened_2.body
|
||||
when eq(_cast_bits_to_bundle_expr_2.tag, UInt<1>(0h0)): @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire _bundle_literal_expr_6: Ty3
|
||||
connect _bundle_literal_expr_6.tag, UInt<1>(0h0)
|
||||
connect _bundle_literal_expr_6.body, UInt<2>(0h0)
|
||||
connect __connect_variant_body_5, _bundle_literal_expr_6 @[module-XXXXXXXXXX.rs 9:1]
|
||||
else:
|
||||
wire __connect_variant_body_6: SInt<2> @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire _cast_bits_to_bundle_expr_4: Ty2
|
||||
wire _cast_bits_to_bundle_expr_flattened_4: Ty2
|
||||
connect _cast_bits_to_bundle_expr_flattened_4.tag, bits(bits(i1.body, 1, 0), 0, 0)
|
||||
connect _cast_bits_to_bundle_expr_4.tag, _cast_bits_to_bundle_expr_flattened_4.tag
|
||||
connect _cast_bits_to_bundle_expr_flattened_4.body, bits(bits(i1.body, 1, 0), 1, 1)
|
||||
connect _cast_bits_to_bundle_expr_4.body, _cast_bits_to_bundle_expr_flattened_4.body
|
||||
; connect different types:
|
||||
; lhs: SInt<2>
|
||||
; rhs: SInt<1>
|
||||
connect __connect_variant_body_6, asSInt(bits(_cast_bits_to_bundle_expr_4.body, 0, 0)) @[module-XXXXXXXXXX.rs 9:1]
|
||||
connect __connect_variant_body_6, asSInt(bits(_cast_bits_to_bundle_expr_2.body, 0, 0)) @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire _bundle_literal_expr_7: Ty3
|
||||
connect _bundle_literal_expr_7.tag, UInt<1>(0h1)
|
||||
connect _bundle_literal_expr_7.body, asUInt(__connect_variant_body_6)
|
||||
|
|
@ -4225,13 +4095,13 @@ circuit check_enum_connect_any:
|
|||
connect o2, _bundle_literal_expr_8 @[module-XXXXXXXXXX.rs 9:1]
|
||||
else:
|
||||
wire __connect_variant_body_7: Ty4 @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire _cast_bits_to_bundle_expr_5: Ty4
|
||||
wire _cast_bits_to_bundle_expr_flattened_5: Ty4
|
||||
connect _cast_bits_to_bundle_expr_flattened_5.tag, bits(bits(i1.body, 0, 0), 0, 0)
|
||||
connect _cast_bits_to_bundle_expr_5.tag, _cast_bits_to_bundle_expr_flattened_5.tag
|
||||
connect _cast_bits_to_bundle_expr_flattened_5.body, UInt<0>(0)
|
||||
connect _cast_bits_to_bundle_expr_5.body, _cast_bits_to_bundle_expr_flattened_5.body
|
||||
connect __connect_variant_body_7, _cast_bits_to_bundle_expr_5 @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire _cast_bits_to_bundle_expr_3: Ty4
|
||||
wire _cast_bits_to_bundle_expr_flattened_3: Ty4
|
||||
connect _cast_bits_to_bundle_expr_flattened_3.tag, bits(bits(i1.body, 0, 0), 0, 0)
|
||||
connect _cast_bits_to_bundle_expr_3.tag, _cast_bits_to_bundle_expr_flattened_3.tag
|
||||
connect _cast_bits_to_bundle_expr_flattened_3.body, UInt<0>(0)
|
||||
connect _cast_bits_to_bundle_expr_3.body, _cast_bits_to_bundle_expr_flattened_3.body
|
||||
connect __connect_variant_body_7, _cast_bits_to_bundle_expr_3 @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire _bundle_literal_expr_9: Ty1
|
||||
connect _bundle_literal_expr_9.tag, UInt<2>(0h2)
|
||||
wire _cast_bundle_to_bits_expr_3: Ty4
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue