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WIP: add cpu::test::decode_and_run_single_insn and some formal tests of running PowerISA instructions #15

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programmerjake wants to merge 7 commits from programmerjake/cpu:decode-and-test-harness into master
pull from: programmerjake/cpu:decode-and-test-harness
merge into: libre-chip:master
Conversation 0 Commits 7 Files changed 23 +5756 -89702
programmerjake commented 2026-06-01 08:11:18 +00:00
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Add a simple HDL module that decodes a single instruction and then runs it one µOp at a time, intended for testing the Units in formal proofs.

Formal tests for instructions so far:

  • add r3, r3, r4 -- the test takes a long time to run, so IDK if it works yet. Conversion to FIRRTL is very slow, so that needs to be fixed first, IDK how fast the actual formal proof using SymbiYosys is since I didn't want to wait long enough to start that.
Add a simple HDL module that decodes a single instruction and then runs it one µOp at a time, intended for testing the Units in formal proofs. Formal tests for instructions so far: * `add r3, r3, r4` -- the test takes a long time to run, so IDK if it works yet. Conversion to FIRRTL is very slow, so that needs to be fixed first, IDK how fast the actual formal proof using SymbiYosys is since I didn't want to wait long enough to start that.
programmerjake added 4 commits 2026-06-01 08:11:18 +00:00
programmerjake added 3 commits 2026-06-02 08:39:21 +00:00
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Reference: libre-chip/cpu#15
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