Add more caching, reduce the number of duplicate wires in generated FIRRTL, and make Module verification check that expressions are visible #76
5 changed files with 996 additions and 627 deletions
File diff suppressed because it is too large
Load diff
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@ -8,7 +8,7 @@ use crate::{
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clock::{Clock, ClockDomain},
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enum_::{Enum, EnumMatchVariantsIter, EnumType},
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expr::{
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Expr, Flow, ToExpr, ValueType,
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Expr, ExprEnum, Flow, ToExpr, ValueType,
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ops::VariantAccess,
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target::{
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GetTarget, Target, TargetBase, TargetPathArrayElement, TargetPathBundleField,
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@ -20,6 +20,7 @@ use crate::{
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int::{Bool, DynSize, Size},
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intern::{Intern, Interned},
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memory::{Mem, MemBuilder, MemBuilderTarget, PortName},
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module::transform::visit::{Visit, Visitor},
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platform::PlatformIOBuilder,
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reg::Reg,
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reset::{AsyncReset, Reset, ResetType, ResetTypeDispatch, SyncReset},
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@ -1598,9 +1599,54 @@ impl TargetState {
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}
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}
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struct VisibleExprsStack {
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buf: Vec<HashSet<ExprEnum>>,
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len: usize,
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}
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impl VisibleExprsStack {
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fn top(&mut self) -> &mut HashSet<ExprEnum> {
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&mut self.buf[self.len - 1]
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}
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fn slice(&self) -> &[HashSet<ExprEnum>] {
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&self.buf[..self.len]
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}
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fn contains(&self, v: &ExprEnum) -> bool {
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self.slice().iter().any(|i| i.contains(v))
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}
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fn push_empty(&mut self) {
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#[cold]
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fn push_empty_cold(stack: &mut VisibleExprsStack) {
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stack.buf.push(HashSet::default());
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assert_eq!(stack.buf.len(), stack.len)
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}
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self.len += 1;
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if self.len > self.buf.len() {
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push_empty_cold(self)
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}
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}
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fn pop(&mut self) {
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let Some(new_len) = self.len.checked_sub(1) else {
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unreachable!("visible exprs stack underflow");
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};
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self.buf[new_len].clear();
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self.len = new_len;
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}
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}
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impl Default for VisibleExprsStack {
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fn default() -> Self {
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Self {
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buf: Vec::new(),
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len: 0,
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}
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}
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}
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struct AssertValidityState {
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module: Module<Bundle>,
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blocks: Vec<Block>,
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visible_exprs: VisibleExprsStack,
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target_states: HashMap<Interned<TargetBase>, TargetState>,
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}
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@ -1771,6 +1817,7 @@ impl AssertValidityState {
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}
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}
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}
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#[track_caller]
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fn process_conditional_sub_blocks(
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&mut self,
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parent_block: usize,
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@ -1784,17 +1831,40 @@ impl AssertValidityState {
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}
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}
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#[track_caller]
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fn assert_expr_validity<T: Type>(&mut self, expr: Expr<T>, source_location: SourceLocation) {
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let mut visitor = AssertExprValidity { state: self };
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match visitor.visit_expr(&expr) {
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Ok(()) => {}
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Err(e) => match e {
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InvalidExpr::ExprIsNotVisible(expr) => {
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if let Some(target) = expr.target() {
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panic!(
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"at {source_location}: expression isn't visible here, it's defined:\n\
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at {}: {expr:?}",
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target.base().source_location(),
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);
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} else {
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panic!("at {source_location}: expression isn't visible here: {expr:?}");
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}
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}
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},
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}
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}
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#[track_caller]
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fn assert_subtree_validity(&mut self, block: usize) {
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self.visible_exprs.push_empty();
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let module = self.module;
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if block == 0 {
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for module_io in &*module.module_io {
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self.insert_new_base(TargetBase::intern_sized(module_io.module_io.into()), block);
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self.visible_exprs.top().insert(module_io.module_io.into());
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}
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}
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let Block { memories, stmts } = self.blocks[block];
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for m in memories {
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for port in m.ports() {
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self.insert_new_base(TargetBase::intern_sized(port.into()), block);
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self.visible_exprs.top().insert(port.into());
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}
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}
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for stmt in stmts {
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@ -1808,44 +1878,104 @@ impl AssertValidityState {
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} = connect;
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self.set_connect_side_written(lhs, source_location, true, block);
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self.set_connect_side_written(rhs, source_location, false, block);
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self.assert_expr_validity(lhs, source_location);
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self.assert_expr_validity(rhs, source_location);
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}
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Stmt::Formal(formal) => {
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let StmtFormal {
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kind: _,
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clk,
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pred,
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en,
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text: _,
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source_location,
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} = formal;
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self.assert_expr_validity(clk, source_location);
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self.assert_expr_validity(pred, source_location);
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self.assert_expr_validity(en, source_location);
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}
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Stmt::Formal(_) => {}
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Stmt::If(if_stmt) => {
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let sub_blocks = if_stmt.blocks.map(|block| self.make_block_index(block));
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let StmtIf {
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cond,
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source_location,
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blocks: sub_blocks,
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} = if_stmt;
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self.assert_expr_validity(cond, source_location);
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let sub_blocks = sub_blocks.map(|block| self.make_block_index(block));
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self.process_conditional_sub_blocks(block, sub_blocks)
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}
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Stmt::Match(match_stmt) => {
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match_stmt.assert_validity();
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let StmtMatch {
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expr,
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source_location,
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blocks: sub_blocks,
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} = match_stmt;
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self.assert_expr_validity(expr, source_location);
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let sub_blocks = Vec::from_iter(
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match_stmt
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.blocks
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sub_blocks
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.into_iter()
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.map(|block| self.make_block_index(block)),
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);
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self.process_conditional_sub_blocks(block, sub_blocks.iter().copied())
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self.visible_exprs.push_empty();
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let visible_exprs_top = self.visible_exprs.top();
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for variant_index in 0..expr.ty().variants().len() {
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visible_exprs_top
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.insert(<VariantAccess>::new_by_index(expr, variant_index).into());
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}
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self.process_conditional_sub_blocks(block, sub_blocks.iter().copied());
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self.visible_exprs.pop();
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}
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Stmt::Declaration(StmtDeclaration::Wire(StmtWire {
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annotations: _,
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wire,
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})) => self.insert_new_base(TargetBase::intern_sized(wire.into()), block),
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})) => {
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self.insert_new_base(TargetBase::intern_sized(wire.into()), block);
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self.visible_exprs.top().insert(wire.into());
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}
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Stmt::Declaration(StmtDeclaration::Reg(StmtReg {
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annotations: _,
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reg,
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})) => self.insert_new_base(TargetBase::intern_sized(reg.into()), block),
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})) => {
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self.assert_expr_validity(reg.clock_domain(), reg.source_location());
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if let Some(init) = reg.init() {
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self.assert_expr_validity(init, reg.source_location());
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}
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self.insert_new_base(TargetBase::intern_sized(reg.into()), block);
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self.visible_exprs.top().insert(reg.into());
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}
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Stmt::Declaration(StmtDeclaration::RegSync(StmtReg {
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annotations: _,
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reg,
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})) => self.insert_new_base(TargetBase::intern_sized(reg.into()), block),
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})) => {
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self.assert_expr_validity(reg.clock_domain(), reg.source_location());
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if let Some(init) = reg.init() {
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self.assert_expr_validity(init, reg.source_location());
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}
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self.insert_new_base(TargetBase::intern_sized(reg.into()), block);
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self.visible_exprs.top().insert(reg.into());
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}
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Stmt::Declaration(StmtDeclaration::RegAsync(StmtReg {
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annotations: _,
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reg,
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})) => self.insert_new_base(TargetBase::intern_sized(reg.into()), block),
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})) => {
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self.assert_expr_validity(reg.clock_domain(), reg.source_location());
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if let Some(init) = reg.init() {
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self.assert_expr_validity(init, reg.source_location());
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}
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self.insert_new_base(TargetBase::intern_sized(reg.into()), block);
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self.visible_exprs.top().insert(reg.into());
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}
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Stmt::Declaration(StmtDeclaration::Instance(StmtInstance {
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annotations: _,
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instance,
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})) => self.insert_new_base(TargetBase::intern_sized(instance.into()), block),
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})) => {
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self.insert_new_base(TargetBase::intern_sized(instance.into()), block);
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self.visible_exprs.top().insert(instance.into());
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}
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}
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}
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self.visible_exprs.pop();
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}
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#[track_caller]
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fn assert_validity(&mut self) {
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@ -1874,6 +2004,140 @@ impl AssertValidityState {
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}
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}
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struct AssertExprValidity<'a> {
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state: &'a mut AssertValidityState,
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}
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enum InvalidExpr {
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ExprIsNotVisible(Expr<CanonicalType>),
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}
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impl transform::visit::Visitor for AssertExprValidity<'_> {
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type Error = InvalidExpr;
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fn visit_expr_enum(&mut self, v: &ExprEnum) -> Result<(), Self::Error> {
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match v {
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ExprEnum::UIntLiteral(_)
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| ExprEnum::SIntLiteral(_)
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| ExprEnum::BoolLiteral(_)
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| ExprEnum::PhantomConst(_)
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| ExprEnum::BundleLiteral(_)
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| ExprEnum::ArrayLiteral(_)
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| ExprEnum::EnumLiteral(_)
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| ExprEnum::Uninit(_)
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| ExprEnum::NotU(_)
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| ExprEnum::NotS(_)
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| ExprEnum::NotB(_)
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| ExprEnum::Neg(_)
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| ExprEnum::BitAndU(_)
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| ExprEnum::BitAndS(_)
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| ExprEnum::BitAndB(_)
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| ExprEnum::BitOrU(_)
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| ExprEnum::BitOrS(_)
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| ExprEnum::BitOrB(_)
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| ExprEnum::BitXorU(_)
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| ExprEnum::BitXorS(_)
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| ExprEnum::BitXorB(_)
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| ExprEnum::AddU(_)
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| ExprEnum::AddS(_)
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| ExprEnum::SubU(_)
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| ExprEnum::SubS(_)
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| ExprEnum::MulU(_)
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| ExprEnum::MulS(_)
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| ExprEnum::DivU(_)
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| ExprEnum::DivS(_)
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| ExprEnum::RemU(_)
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| ExprEnum::RemS(_)
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| ExprEnum::DynShlU(_)
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| ExprEnum::DynShlS(_)
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| ExprEnum::DynShrU(_)
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| ExprEnum::DynShrS(_)
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| ExprEnum::FixedShlU(_)
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| ExprEnum::FixedShlS(_)
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| ExprEnum::FixedShrU(_)
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| ExprEnum::FixedShrS(_)
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| ExprEnum::CmpLtB(_)
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| ExprEnum::CmpLeB(_)
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| ExprEnum::CmpGtB(_)
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| ExprEnum::CmpGeB(_)
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| ExprEnum::CmpEqB(_)
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| ExprEnum::CmpNeB(_)
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| ExprEnum::CmpLtU(_)
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| ExprEnum::CmpLeU(_)
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| ExprEnum::CmpGtU(_)
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| ExprEnum::CmpGeU(_)
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| ExprEnum::CmpEqU(_)
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| ExprEnum::CmpNeU(_)
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| ExprEnum::CmpLtS(_)
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| ExprEnum::CmpLeS(_)
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| ExprEnum::CmpGtS(_)
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| ExprEnum::CmpGeS(_)
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| ExprEnum::CmpEqS(_)
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| ExprEnum::CmpNeS(_)
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| ExprEnum::CastUIntToUInt(_)
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| ExprEnum::CastUIntToSInt(_)
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| ExprEnum::CastSIntToUInt(_)
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| ExprEnum::CastSIntToSInt(_)
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| ExprEnum::CastBoolToUInt(_)
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| ExprEnum::CastBoolToSInt(_)
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| ExprEnum::CastUIntToBool(_)
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| ExprEnum::CastSIntToBool(_)
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| ExprEnum::CastBoolToSyncReset(_)
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| ExprEnum::CastUIntToSyncReset(_)
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| ExprEnum::CastSIntToSyncReset(_)
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| ExprEnum::CastBoolToAsyncReset(_)
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| ExprEnum::CastUIntToAsyncReset(_)
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| ExprEnum::CastSIntToAsyncReset(_)
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| ExprEnum::CastSyncResetToBool(_)
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| ExprEnum::CastSyncResetToUInt(_)
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| ExprEnum::CastSyncResetToSInt(_)
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| ExprEnum::CastSyncResetToReset(_)
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| ExprEnum::CastAsyncResetToBool(_)
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| ExprEnum::CastAsyncResetToUInt(_)
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| ExprEnum::CastAsyncResetToSInt(_)
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| ExprEnum::CastAsyncResetToReset(_)
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| ExprEnum::CastResetToBool(_)
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| ExprEnum::CastResetToUInt(_)
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| ExprEnum::CastResetToSInt(_)
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| ExprEnum::CastBoolToClock(_)
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| ExprEnum::CastUIntToClock(_)
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| ExprEnum::CastSIntToClock(_)
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| ExprEnum::CastClockToBool(_)
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| ExprEnum::CastClockToUInt(_)
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| ExprEnum::CastClockToSInt(_)
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| ExprEnum::FieldAccess(_)
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| ExprEnum::ArrayIndex(_)
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| ExprEnum::DynArrayIndex(_)
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| ExprEnum::ReduceBitAndU(_)
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| ExprEnum::ReduceBitAndS(_)
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| ExprEnum::ReduceBitOrU(_)
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| ExprEnum::ReduceBitOrS(_)
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| ExprEnum::ReduceBitXorU(_)
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| ExprEnum::ReduceBitXorS(_)
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| ExprEnum::SliceUInt(_)
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| ExprEnum::SliceSInt(_)
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| ExprEnum::CastToBits(_)
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| ExprEnum::CastBitsTo(_)
|
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| ExprEnum::ToTraceAsString(_)
|
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| ExprEnum::TraceAsStringAsInner(_) => v.default_visit(self),
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ExprEnum::VariantAccess(_)
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| ExprEnum::ModuleIO(_)
|
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| ExprEnum::Instance(_)
|
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| ExprEnum::Wire(_)
|
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| ExprEnum::Reg(_)
|
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| ExprEnum::RegSync(_)
|
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| ExprEnum::RegAsync(_)
|
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| ExprEnum::MemPort(_) => {
|
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if self.state.visible_exprs.contains(v) {
|
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// no need to visit inner expressions, we already checked them before adding them to visible_exprs
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Ok(())
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} else {
|
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Err(InvalidExpr::ExprIsNotVisible(v.to_expr()))
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}
|
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}
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}
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}
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}
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impl<T: BundleType> Module<T> {
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/// you generally should use the [`#[hdl_module]`][`crate::hdl_module`] proc-macro and [`ModuleBuilder`] instead
|
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#[track_caller]
|
||||
|
|
@ -1999,6 +2263,7 @@ impl<T: BundleType> Module<T> {
|
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AssertValidityState {
|
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module: self.canonical(),
|
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blocks: vec![],
|
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visible_exprs: VisibleExprsStack::default(),
|
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target_states: HashMap::with_capacity_and_hasher(64, Default::default()),
|
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}
|
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.assert_validity();
|
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|
|
|
|||
|
|
@ -96,6 +96,7 @@ enum EnumTypeState {
|
|||
|
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struct ModuleState {
|
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module_name: NameId,
|
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expr_cache: HashMap<ExprEnum, ExprEnum>,
|
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}
|
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|
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impl ModuleState {
|
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|
|
@ -675,6 +676,7 @@ impl Folder for State {
|
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fn fold_module<T: BundleType>(&mut self, v: Module<T>) -> Result<Module<T>, Self::Error> {
|
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self.module_state_stack.push(ModuleState {
|
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module_name: v.name_id(),
|
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expr_cache: HashMap::default(),
|
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});
|
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let retval = Fold::default_fold(v, self);
|
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self.module_state_stack.pop();
|
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|
|
@ -682,30 +684,39 @@ impl Folder for State {
|
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}
|
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|
||||
fn fold_expr_enum(&mut self, op: ExprEnum) -> Result<ExprEnum, Self::Error> {
|
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match op {
|
||||
if let Some(folded_op) = self
|
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.module_state_stack
|
||||
.last()
|
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.expect("known to be in module")
|
||||
.expr_cache
|
||||
.get(&op)
|
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{
|
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return Ok(*folded_op);
|
||||
}
|
||||
let folded_op = match op {
|
||||
ExprEnum::EnumLiteral(op) => {
|
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let folded_variant_value = op.variant_value().map(|v| v.fold(self)).transpose()?;
|
||||
Ok(*Expr::expr_enum(self.handle_enum_literal(
|
||||
*Expr::expr_enum(self.handle_enum_literal(
|
||||
op.ty(),
|
||||
op.variant_index(),
|
||||
folded_variant_value,
|
||||
)?))
|
||||
)?)
|
||||
}
|
||||
ExprEnum::VariantAccess(op) => {
|
||||
let folded_base_expr = Expr::canonical(op.base()).fold(self)?;
|
||||
Ok(*Expr::expr_enum(self.handle_variant_access(
|
||||
*Expr::expr_enum(self.handle_variant_access(
|
||||
op.base().ty(),
|
||||
folded_base_expr,
|
||||
op.variant_index(),
|
||||
)?))
|
||||
)?)
|
||||
}
|
||||
ExprEnum::MemPort(mem_port) => Ok(
|
||||
ExprEnum::MemPort(mem_port) => {
|
||||
if let Some(&wire) = self.replacement_mem_ports.get(&mem_port) {
|
||||
ExprEnum::Wire(wire)
|
||||
} else {
|
||||
ExprEnum::MemPort(mem_port.fold(self)?)
|
||||
},
|
||||
),
|
||||
}
|
||||
}
|
||||
ExprEnum::UIntLiteral(_)
|
||||
| ExprEnum::SIntLiteral(_)
|
||||
| ExprEnum::BoolLiteral(_)
|
||||
|
|
@ -813,8 +824,14 @@ impl Folder for State {
|
|||
| ExprEnum::Wire(_)
|
||||
| ExprEnum::Reg(_)
|
||||
| ExprEnum::RegSync(_)
|
||||
| ExprEnum::RegAsync(_) => op.default_fold(self),
|
||||
}
|
||||
| ExprEnum::RegAsync(_) => op.default_fold(self)?,
|
||||
};
|
||||
self.module_state_stack
|
||||
.last_mut()
|
||||
.expect("known to be in module")
|
||||
.expr_cache
|
||||
.insert(op, folded_op);
|
||||
Ok(folded_op)
|
||||
}
|
||||
|
||||
fn fold_block(&mut self, block: Block) -> Result<Block, Self::Error> {
|
||||
|
|
|
|||
|
|
@ -1309,16 +1309,49 @@ trait TraceAsStringTrait: fmt::Debug + 'static + Send + Sync + SupportsPtrEqWith
|
|||
fn can_substitute_type(&self, new_type: CanonicalType) -> bool;
|
||||
}
|
||||
|
||||
impl<T: Type> TraceAsStringTrait for T {
|
||||
#[derive(Clone, PartialEq, Eq, Hash)]
|
||||
struct TraceAsStringState<T: Type> {
|
||||
ty: Interned<T>,
|
||||
canonical_ty: CanonicalType,
|
||||
}
|
||||
|
||||
impl<T: Type> TraceAsStringState<T> {
|
||||
fn new(ty: Interned<T>) -> Interned<Self> {
|
||||
#[derive(Copy, Clone, PartialEq, Eq, Hash)]
|
||||
struct MyMemoize<T: Type>(PhantomData<T>);
|
||||
impl<T: Type> Memoize for MyMemoize<T> {
|
||||
type Input = Interned<T>;
|
||||
type InputOwned = Interned<T>;
|
||||
type Output = Interned<TraceAsStringState<T>>;
|
||||
|
||||
fn inner(self, input: &Self::Input) -> Self::Output {
|
||||
TraceAsStringState {
|
||||
ty: *input,
|
||||
canonical_ty: input.canonical(),
|
||||
}
|
||||
.intern_sized()
|
||||
}
|
||||
}
|
||||
MyMemoize(PhantomData).get_owned(ty)
|
||||
}
|
||||
}
|
||||
|
||||
impl<T: Type> fmt::Debug for TraceAsStringState<T> {
|
||||
fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
|
||||
self.ty.fmt(f)
|
||||
}
|
||||
}
|
||||
|
||||
impl<T: Type> TraceAsStringTrait for TraceAsStringState<T> {
|
||||
fn trace_fmt(
|
||||
&self,
|
||||
opaque: OpaqueSimValueSlice<'_>,
|
||||
f: &mut fmt::Formatter<'_>,
|
||||
) -> fmt::Result {
|
||||
fmt::Debug::fmt(&Type::sim_value_from_opaque(self, opaque), f)
|
||||
fmt::Debug::fmt(&Type::sim_value_from_opaque(&*self.ty, opaque), f)
|
||||
}
|
||||
fn can_substitute_type(&self, new_type: CanonicalType) -> bool {
|
||||
self.canonical().is_layout_equivalent(new_type)
|
||||
self.canonical_ty.is_layout_equivalent(new_type)
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1374,7 +1407,7 @@ impl<T: Type> TraceAsString<T> {
|
|||
Self {
|
||||
inner_ty: LazyInterned::Interned(inner_ty),
|
||||
trace_as_string: LazyInterned::Interned(Interned::cast_unchecked(
|
||||
inner_ty,
|
||||
TraceAsStringState::new(inner_ty),
|
||||
|v| -> &dyn TraceAsStringTrait { v },
|
||||
)),
|
||||
}
|
||||
|
|
@ -1548,7 +1581,10 @@ impl<T: StaticType> Default for TraceAsStringStaticTypeHelper<T> {
|
|||
|
||||
impl<T: StaticType> From<TraceAsStringStaticTypeHelper<T>> for Interned<dyn TraceAsStringTrait> {
|
||||
fn from(_value: TraceAsStringStaticTypeHelper<T>) -> Self {
|
||||
Interned::cast_unchecked(T::TYPE.intern_sized(), |v| -> &dyn TraceAsStringTrait { v })
|
||||
Interned::cast_unchecked(
|
||||
TraceAsStringState::new(T::TYPE.intern_sized()),
|
||||
|v| -> &dyn TraceAsStringTrait { v },
|
||||
)
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -808,40 +808,8 @@ circuit check_enum_cmp_eq:
|
|||
connect _cast_bits_to_array_expr_flattened_1[2], bits(bits(rhs.body, 2, 0), 2, 2)
|
||||
connect _cast_bits_to_array_expr_1[2], _cast_bits_to_array_expr_flattened_1[2]
|
||||
connect _array_literal_expr[0], eq(_cast_bits_to_array_expr[0], _cast_bits_to_array_expr_1[0])
|
||||
wire _cast_bits_to_array_expr_2: UInt<1>[3]
|
||||
wire _cast_bits_to_array_expr_flattened_2: UInt<1>[3]
|
||||
connect _cast_bits_to_array_expr_flattened_2[0], bits(bits(lhs.body, 2, 0), 0, 0)
|
||||
connect _cast_bits_to_array_expr_2[0], _cast_bits_to_array_expr_flattened_2[0]
|
||||
connect _cast_bits_to_array_expr_flattened_2[1], bits(bits(lhs.body, 2, 0), 1, 1)
|
||||
connect _cast_bits_to_array_expr_2[1], _cast_bits_to_array_expr_flattened_2[1]
|
||||
connect _cast_bits_to_array_expr_flattened_2[2], bits(bits(lhs.body, 2, 0), 2, 2)
|
||||
connect _cast_bits_to_array_expr_2[2], _cast_bits_to_array_expr_flattened_2[2]
|
||||
wire _cast_bits_to_array_expr_3: UInt<1>[3]
|
||||
wire _cast_bits_to_array_expr_flattened_3: UInt<1>[3]
|
||||
connect _cast_bits_to_array_expr_flattened_3[0], bits(bits(rhs.body, 2, 0), 0, 0)
|
||||
connect _cast_bits_to_array_expr_3[0], _cast_bits_to_array_expr_flattened_3[0]
|
||||
connect _cast_bits_to_array_expr_flattened_3[1], bits(bits(rhs.body, 2, 0), 1, 1)
|
||||
connect _cast_bits_to_array_expr_3[1], _cast_bits_to_array_expr_flattened_3[1]
|
||||
connect _cast_bits_to_array_expr_flattened_3[2], bits(bits(rhs.body, 2, 0), 2, 2)
|
||||
connect _cast_bits_to_array_expr_3[2], _cast_bits_to_array_expr_flattened_3[2]
|
||||
connect _array_literal_expr[1], eq(_cast_bits_to_array_expr_2[1], _cast_bits_to_array_expr_3[1])
|
||||
wire _cast_bits_to_array_expr_4: UInt<1>[3]
|
||||
wire _cast_bits_to_array_expr_flattened_4: UInt<1>[3]
|
||||
connect _cast_bits_to_array_expr_flattened_4[0], bits(bits(lhs.body, 2, 0), 0, 0)
|
||||
connect _cast_bits_to_array_expr_4[0], _cast_bits_to_array_expr_flattened_4[0]
|
||||
connect _cast_bits_to_array_expr_flattened_4[1], bits(bits(lhs.body, 2, 0), 1, 1)
|
||||
connect _cast_bits_to_array_expr_4[1], _cast_bits_to_array_expr_flattened_4[1]
|
||||
connect _cast_bits_to_array_expr_flattened_4[2], bits(bits(lhs.body, 2, 0), 2, 2)
|
||||
connect _cast_bits_to_array_expr_4[2], _cast_bits_to_array_expr_flattened_4[2]
|
||||
wire _cast_bits_to_array_expr_5: UInt<1>[3]
|
||||
wire _cast_bits_to_array_expr_flattened_5: UInt<1>[3]
|
||||
connect _cast_bits_to_array_expr_flattened_5[0], bits(bits(rhs.body, 2, 0), 0, 0)
|
||||
connect _cast_bits_to_array_expr_5[0], _cast_bits_to_array_expr_flattened_5[0]
|
||||
connect _cast_bits_to_array_expr_flattened_5[1], bits(bits(rhs.body, 2, 0), 1, 1)
|
||||
connect _cast_bits_to_array_expr_5[1], _cast_bits_to_array_expr_flattened_5[1]
|
||||
connect _cast_bits_to_array_expr_flattened_5[2], bits(bits(rhs.body, 2, 0), 2, 2)
|
||||
connect _cast_bits_to_array_expr_5[2], _cast_bits_to_array_expr_flattened_5[2]
|
||||
connect _array_literal_expr[2], eq(_cast_bits_to_array_expr_4[2], _cast_bits_to_array_expr_5[2])
|
||||
connect _array_literal_expr[1], eq(_cast_bits_to_array_expr[1], _cast_bits_to_array_expr_1[1])
|
||||
connect _array_literal_expr[2], eq(_cast_bits_to_array_expr[2], _cast_bits_to_array_expr_1[2])
|
||||
wire _cast_array_to_bits_expr: UInt<1>[3]
|
||||
connect _cast_array_to_bits_expr[0], _array_literal_expr[0]
|
||||
connect _cast_array_to_bits_expr[1], _array_literal_expr[1]
|
||||
|
|
@ -901,40 +869,8 @@ circuit check_enum_cmp_eq:
|
|||
connect _cast_bits_to_array_expr_flattened_1[2], bits(bits(rhs.body, 2, 0), 2, 2)
|
||||
connect _cast_bits_to_array_expr_1[2], _cast_bits_to_array_expr_flattened_1[2]
|
||||
connect _array_literal_expr[0], eq(_cast_bits_to_array_expr[0], _cast_bits_to_array_expr_1[0])
|
||||
wire _cast_bits_to_array_expr_2: UInt<1>[3]
|
||||
wire _cast_bits_to_array_expr_flattened_2: UInt<1>[3]
|
||||
connect _cast_bits_to_array_expr_flattened_2[0], bits(bits(lhs.body, 2, 0), 0, 0)
|
||||
connect _cast_bits_to_array_expr_2[0], _cast_bits_to_array_expr_flattened_2[0]
|
||||
connect _cast_bits_to_array_expr_flattened_2[1], bits(bits(lhs.body, 2, 0), 1, 1)
|
||||
connect _cast_bits_to_array_expr_2[1], _cast_bits_to_array_expr_flattened_2[1]
|
||||
connect _cast_bits_to_array_expr_flattened_2[2], bits(bits(lhs.body, 2, 0), 2, 2)
|
||||
connect _cast_bits_to_array_expr_2[2], _cast_bits_to_array_expr_flattened_2[2]
|
||||
wire _cast_bits_to_array_expr_3: UInt<1>[3]
|
||||
wire _cast_bits_to_array_expr_flattened_3: UInt<1>[3]
|
||||
connect _cast_bits_to_array_expr_flattened_3[0], bits(bits(rhs.body, 2, 0), 0, 0)
|
||||
connect _cast_bits_to_array_expr_3[0], _cast_bits_to_array_expr_flattened_3[0]
|
||||
connect _cast_bits_to_array_expr_flattened_3[1], bits(bits(rhs.body, 2, 0), 1, 1)
|
||||
connect _cast_bits_to_array_expr_3[1], _cast_bits_to_array_expr_flattened_3[1]
|
||||
connect _cast_bits_to_array_expr_flattened_3[2], bits(bits(rhs.body, 2, 0), 2, 2)
|
||||
connect _cast_bits_to_array_expr_3[2], _cast_bits_to_array_expr_flattened_3[2]
|
||||
connect _array_literal_expr[1], eq(_cast_bits_to_array_expr_2[1], _cast_bits_to_array_expr_3[1])
|
||||
wire _cast_bits_to_array_expr_4: UInt<1>[3]
|
||||
wire _cast_bits_to_array_expr_flattened_4: UInt<1>[3]
|
||||
connect _cast_bits_to_array_expr_flattened_4[0], bits(bits(lhs.body, 2, 0), 0, 0)
|
||||
connect _cast_bits_to_array_expr_4[0], _cast_bits_to_array_expr_flattened_4[0]
|
||||
connect _cast_bits_to_array_expr_flattened_4[1], bits(bits(lhs.body, 2, 0), 1, 1)
|
||||
connect _cast_bits_to_array_expr_4[1], _cast_bits_to_array_expr_flattened_4[1]
|
||||
connect _cast_bits_to_array_expr_flattened_4[2], bits(bits(lhs.body, 2, 0), 2, 2)
|
||||
connect _cast_bits_to_array_expr_4[2], _cast_bits_to_array_expr_flattened_4[2]
|
||||
wire _cast_bits_to_array_expr_5: UInt<1>[3]
|
||||
wire _cast_bits_to_array_expr_flattened_5: UInt<1>[3]
|
||||
connect _cast_bits_to_array_expr_flattened_5[0], bits(bits(rhs.body, 2, 0), 0, 0)
|
||||
connect _cast_bits_to_array_expr_5[0], _cast_bits_to_array_expr_flattened_5[0]
|
||||
connect _cast_bits_to_array_expr_flattened_5[1], bits(bits(rhs.body, 2, 0), 1, 1)
|
||||
connect _cast_bits_to_array_expr_5[1], _cast_bits_to_array_expr_flattened_5[1]
|
||||
connect _cast_bits_to_array_expr_flattened_5[2], bits(bits(rhs.body, 2, 0), 2, 2)
|
||||
connect _cast_bits_to_array_expr_5[2], _cast_bits_to_array_expr_flattened_5[2]
|
||||
connect _array_literal_expr[2], eq(_cast_bits_to_array_expr_4[2], _cast_bits_to_array_expr_5[2])
|
||||
connect _array_literal_expr[1], eq(_cast_bits_to_array_expr[1], _cast_bits_to_array_expr_1[1])
|
||||
connect _array_literal_expr[2], eq(_cast_bits_to_array_expr[2], _cast_bits_to_array_expr_1[2])
|
||||
wire _cast_array_to_bits_expr: UInt<1>[3]
|
||||
connect _cast_array_to_bits_expr[0], _array_literal_expr[0]
|
||||
connect _cast_array_to_bits_expr[1], _array_literal_expr[1]
|
||||
|
|
@ -993,40 +929,8 @@ circuit check_enum_cmp_eq:
|
|||
connect _cast_bits_to_array_expr_flattened_1[2], bits(bits(bits(rhs, 9, 2), 2, 0), 2, 2)
|
||||
connect _cast_bits_to_array_expr_1[2], _cast_bits_to_array_expr_flattened_1[2]
|
||||
connect _array_literal_expr[0], eq(_cast_bits_to_array_expr[0], _cast_bits_to_array_expr_1[0])
|
||||
wire _cast_bits_to_array_expr_2: UInt<1>[3]
|
||||
wire _cast_bits_to_array_expr_flattened_2: UInt<1>[3]
|
||||
connect _cast_bits_to_array_expr_flattened_2[0], bits(bits(bits(lhs, 9, 2), 2, 0), 0, 0)
|
||||
connect _cast_bits_to_array_expr_2[0], _cast_bits_to_array_expr_flattened_2[0]
|
||||
connect _cast_bits_to_array_expr_flattened_2[1], bits(bits(bits(lhs, 9, 2), 2, 0), 1, 1)
|
||||
connect _cast_bits_to_array_expr_2[1], _cast_bits_to_array_expr_flattened_2[1]
|
||||
connect _cast_bits_to_array_expr_flattened_2[2], bits(bits(bits(lhs, 9, 2), 2, 0), 2, 2)
|
||||
connect _cast_bits_to_array_expr_2[2], _cast_bits_to_array_expr_flattened_2[2]
|
||||
wire _cast_bits_to_array_expr_3: UInt<1>[3]
|
||||
wire _cast_bits_to_array_expr_flattened_3: UInt<1>[3]
|
||||
connect _cast_bits_to_array_expr_flattened_3[0], bits(bits(bits(rhs, 9, 2), 2, 0), 0, 0)
|
||||
connect _cast_bits_to_array_expr_3[0], _cast_bits_to_array_expr_flattened_3[0]
|
||||
connect _cast_bits_to_array_expr_flattened_3[1], bits(bits(bits(rhs, 9, 2), 2, 0), 1, 1)
|
||||
connect _cast_bits_to_array_expr_3[1], _cast_bits_to_array_expr_flattened_3[1]
|
||||
connect _cast_bits_to_array_expr_flattened_3[2], bits(bits(bits(rhs, 9, 2), 2, 0), 2, 2)
|
||||
connect _cast_bits_to_array_expr_3[2], _cast_bits_to_array_expr_flattened_3[2]
|
||||
connect _array_literal_expr[1], eq(_cast_bits_to_array_expr_2[1], _cast_bits_to_array_expr_3[1])
|
||||
wire _cast_bits_to_array_expr_4: UInt<1>[3]
|
||||
wire _cast_bits_to_array_expr_flattened_4: UInt<1>[3]
|
||||
connect _cast_bits_to_array_expr_flattened_4[0], bits(bits(bits(lhs, 9, 2), 2, 0), 0, 0)
|
||||
connect _cast_bits_to_array_expr_4[0], _cast_bits_to_array_expr_flattened_4[0]
|
||||
connect _cast_bits_to_array_expr_flattened_4[1], bits(bits(bits(lhs, 9, 2), 2, 0), 1, 1)
|
||||
connect _cast_bits_to_array_expr_4[1], _cast_bits_to_array_expr_flattened_4[1]
|
||||
connect _cast_bits_to_array_expr_flattened_4[2], bits(bits(bits(lhs, 9, 2), 2, 0), 2, 2)
|
||||
connect _cast_bits_to_array_expr_4[2], _cast_bits_to_array_expr_flattened_4[2]
|
||||
wire _cast_bits_to_array_expr_5: UInt<1>[3]
|
||||
wire _cast_bits_to_array_expr_flattened_5: UInt<1>[3]
|
||||
connect _cast_bits_to_array_expr_flattened_5[0], bits(bits(bits(rhs, 9, 2), 2, 0), 0, 0)
|
||||
connect _cast_bits_to_array_expr_5[0], _cast_bits_to_array_expr_flattened_5[0]
|
||||
connect _cast_bits_to_array_expr_flattened_5[1], bits(bits(bits(rhs, 9, 2), 2, 0), 1, 1)
|
||||
connect _cast_bits_to_array_expr_5[1], _cast_bits_to_array_expr_flattened_5[1]
|
||||
connect _cast_bits_to_array_expr_flattened_5[2], bits(bits(bits(rhs, 9, 2), 2, 0), 2, 2)
|
||||
connect _cast_bits_to_array_expr_5[2], _cast_bits_to_array_expr_flattened_5[2]
|
||||
connect _array_literal_expr[2], eq(_cast_bits_to_array_expr_4[2], _cast_bits_to_array_expr_5[2])
|
||||
connect _array_literal_expr[1], eq(_cast_bits_to_array_expr[1], _cast_bits_to_array_expr_1[1])
|
||||
connect _array_literal_expr[2], eq(_cast_bits_to_array_expr[2], _cast_bits_to_array_expr_1[2])
|
||||
wire _cast_array_to_bits_expr: UInt<1>[3]
|
||||
connect _cast_array_to_bits_expr[0], _array_literal_expr[0]
|
||||
connect _cast_array_to_bits_expr[1], _array_literal_expr[1]
|
||||
|
|
@ -3925,21 +3829,10 @@ circuit check_enum_connect_any:
|
|||
connect __connect_variant_body_1, _bundle_literal_expr_1 @[module-XXXXXXXXXX.rs 8:1]
|
||||
HdlSome:
|
||||
wire __connect_variant_body_2: SInt<1> @[module-XXXXXXXXXX.rs 8:1]
|
||||
wire _cast_bits_to_bundle_expr_1: Ty5
|
||||
wire _cast_bits_to_bundle_expr_flattened_1: Ty6
|
||||
connect _cast_bits_to_bundle_expr_flattened_1.tag, bits(bits(i2.body, 2, 0), 0, 0)
|
||||
wire _cast_bits_to_enum_expr_1: Ty3
|
||||
when eq(UInt<1>(0), tail(_cast_bits_to_bundle_expr_flattened_1.tag, 0)):
|
||||
connect _cast_bits_to_enum_expr_1, {|HdlNone, HdlSome|}(HdlNone)
|
||||
else:
|
||||
connect _cast_bits_to_enum_expr_1, {|HdlNone, HdlSome|}(HdlSome)
|
||||
connect _cast_bits_to_bundle_expr_1.tag, _cast_bits_to_enum_expr_1
|
||||
connect _cast_bits_to_bundle_expr_flattened_1.body, bits(bits(i2.body, 2, 0), 2, 1)
|
||||
connect _cast_bits_to_bundle_expr_1.body, _cast_bits_to_bundle_expr_flattened_1.body
|
||||
; connect different types:
|
||||
; lhs: SInt<1>
|
||||
; rhs: SInt<2>
|
||||
connect __connect_variant_body_2, asSInt(bits(_cast_bits_to_bundle_expr_1.body, 1, 0)) @[module-XXXXXXXXXX.rs 8:1]
|
||||
connect __connect_variant_body_2, asSInt(bits(_cast_bits_to_bundle_expr.body, 1, 0)) @[module-XXXXXXXXXX.rs 8:1]
|
||||
wire _bundle_literal_expr_2: Ty4
|
||||
connect _bundle_literal_expr_2.tag, {|HdlNone, HdlSome|}(HdlSome)
|
||||
connect _bundle_literal_expr_2.body, asUInt(__connect_variant_body_2)
|
||||
|
|
@ -3961,18 +3854,18 @@ circuit check_enum_connect_any:
|
|||
connect o1, _bundle_literal_expr_3 @[module-XXXXXXXXXX.rs 8:1]
|
||||
C:
|
||||
wire __connect_variant_body_3: Ty8 @[module-XXXXXXXXXX.rs 8:1]
|
||||
wire _cast_bits_to_bundle_expr_2: Ty8
|
||||
wire _cast_bits_to_bundle_expr_flattened_2: Ty9
|
||||
connect _cast_bits_to_bundle_expr_flattened_2.tag, bits(bits(i2.body, 0, 0), 0, 0)
|
||||
wire _cast_bits_to_enum_expr_2: Ty3
|
||||
when eq(UInt<1>(0), tail(_cast_bits_to_bundle_expr_flattened_2.tag, 0)):
|
||||
connect _cast_bits_to_enum_expr_2, {|HdlNone, HdlSome|}(HdlNone)
|
||||
wire _cast_bits_to_bundle_expr_1: Ty8
|
||||
wire _cast_bits_to_bundle_expr_flattened_1: Ty9
|
||||
connect _cast_bits_to_bundle_expr_flattened_1.tag, bits(bits(i2.body, 0, 0), 0, 0)
|
||||
wire _cast_bits_to_enum_expr_1: Ty3
|
||||
when eq(UInt<1>(0), tail(_cast_bits_to_bundle_expr_flattened_1.tag, 0)):
|
||||
connect _cast_bits_to_enum_expr_1, {|HdlNone, HdlSome|}(HdlNone)
|
||||
else:
|
||||
connect _cast_bits_to_enum_expr_2, {|HdlNone, HdlSome|}(HdlSome)
|
||||
connect _cast_bits_to_bundle_expr_2.tag, _cast_bits_to_enum_expr_2
|
||||
connect _cast_bits_to_bundle_expr_flattened_2.body, UInt<0>(0)
|
||||
connect _cast_bits_to_bundle_expr_2.body, _cast_bits_to_bundle_expr_flattened_2.body
|
||||
connect __connect_variant_body_3, _cast_bits_to_bundle_expr_2 @[module-XXXXXXXXXX.rs 8:1]
|
||||
connect _cast_bits_to_enum_expr_1, {|HdlNone, HdlSome|}(HdlSome)
|
||||
connect _cast_bits_to_bundle_expr_1.tag, _cast_bits_to_enum_expr_1
|
||||
connect _cast_bits_to_bundle_expr_flattened_1.body, UInt<0>(0)
|
||||
connect _cast_bits_to_bundle_expr_1.body, _cast_bits_to_bundle_expr_flattened_1.body
|
||||
connect __connect_variant_body_3, _cast_bits_to_bundle_expr_1 @[module-XXXXXXXXXX.rs 8:1]
|
||||
wire _bundle_literal_expr_4: Ty1
|
||||
connect _bundle_literal_expr_4.tag, {|A, B, C|}(C)
|
||||
wire _cast_bundle_to_bits_expr_1: Ty9
|
||||
|
|
@ -4001,18 +3894,18 @@ circuit check_enum_connect_any:
|
|||
connect o2, _bundle_literal_expr_5 @[module-XXXXXXXXXX.rs 9:1]
|
||||
B:
|
||||
wire __connect_variant_body_5: Ty5 @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire _cast_bits_to_bundle_expr_3: Ty4
|
||||
wire _cast_bits_to_bundle_expr_flattened_3: Ty7
|
||||
connect _cast_bits_to_bundle_expr_flattened_3.tag, bits(bits(i1.body, 1, 0), 0, 0)
|
||||
wire _cast_bits_to_enum_expr_3: Ty3
|
||||
when eq(UInt<1>(0), tail(_cast_bits_to_bundle_expr_flattened_3.tag, 0)):
|
||||
connect _cast_bits_to_enum_expr_3, {|HdlNone, HdlSome|}(HdlNone)
|
||||
wire _cast_bits_to_bundle_expr_2: Ty4
|
||||
wire _cast_bits_to_bundle_expr_flattened_2: Ty7
|
||||
connect _cast_bits_to_bundle_expr_flattened_2.tag, bits(bits(i1.body, 1, 0), 0, 0)
|
||||
wire _cast_bits_to_enum_expr_2: Ty3
|
||||
when eq(UInt<1>(0), tail(_cast_bits_to_bundle_expr_flattened_2.tag, 0)):
|
||||
connect _cast_bits_to_enum_expr_2, {|HdlNone, HdlSome|}(HdlNone)
|
||||
else:
|
||||
connect _cast_bits_to_enum_expr_3, {|HdlNone, HdlSome|}(HdlSome)
|
||||
connect _cast_bits_to_bundle_expr_3.tag, _cast_bits_to_enum_expr_3
|
||||
connect _cast_bits_to_bundle_expr_flattened_3.body, bits(bits(i1.body, 1, 0), 1, 1)
|
||||
connect _cast_bits_to_bundle_expr_3.body, _cast_bits_to_bundle_expr_flattened_3.body
|
||||
match _cast_bits_to_bundle_expr_3.tag: @[module-XXXXXXXXXX.rs 9:1]
|
||||
connect _cast_bits_to_enum_expr_2, {|HdlNone, HdlSome|}(HdlSome)
|
||||
connect _cast_bits_to_bundle_expr_2.tag, _cast_bits_to_enum_expr_2
|
||||
connect _cast_bits_to_bundle_expr_flattened_2.body, bits(bits(i1.body, 1, 0), 1, 1)
|
||||
connect _cast_bits_to_bundle_expr_2.body, _cast_bits_to_bundle_expr_flattened_2.body
|
||||
match _cast_bits_to_bundle_expr_2.tag: @[module-XXXXXXXXXX.rs 9:1]
|
||||
HdlNone:
|
||||
wire _bundle_literal_expr_6: Ty5
|
||||
connect _bundle_literal_expr_6.tag, {|HdlNone, HdlSome|}(HdlNone)
|
||||
|
|
@ -4020,21 +3913,10 @@ circuit check_enum_connect_any:
|
|||
connect __connect_variant_body_5, _bundle_literal_expr_6 @[module-XXXXXXXXXX.rs 9:1]
|
||||
HdlSome:
|
||||
wire __connect_variant_body_6: SInt<2> @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire _cast_bits_to_bundle_expr_4: Ty4
|
||||
wire _cast_bits_to_bundle_expr_flattened_4: Ty7
|
||||
connect _cast_bits_to_bundle_expr_flattened_4.tag, bits(bits(i1.body, 1, 0), 0, 0)
|
||||
wire _cast_bits_to_enum_expr_4: Ty3
|
||||
when eq(UInt<1>(0), tail(_cast_bits_to_bundle_expr_flattened_4.tag, 0)):
|
||||
connect _cast_bits_to_enum_expr_4, {|HdlNone, HdlSome|}(HdlNone)
|
||||
else:
|
||||
connect _cast_bits_to_enum_expr_4, {|HdlNone, HdlSome|}(HdlSome)
|
||||
connect _cast_bits_to_bundle_expr_4.tag, _cast_bits_to_enum_expr_4
|
||||
connect _cast_bits_to_bundle_expr_flattened_4.body, bits(bits(i1.body, 1, 0), 1, 1)
|
||||
connect _cast_bits_to_bundle_expr_4.body, _cast_bits_to_bundle_expr_flattened_4.body
|
||||
; connect different types:
|
||||
; lhs: SInt<2>
|
||||
; rhs: SInt<1>
|
||||
connect __connect_variant_body_6, asSInt(bits(_cast_bits_to_bundle_expr_4.body, 0, 0)) @[module-XXXXXXXXXX.rs 9:1]
|
||||
connect __connect_variant_body_6, asSInt(bits(_cast_bits_to_bundle_expr_2.body, 0, 0)) @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire _bundle_literal_expr_7: Ty5
|
||||
connect _bundle_literal_expr_7.tag, {|HdlNone, HdlSome|}(HdlSome)
|
||||
connect _bundle_literal_expr_7.body, asUInt(__connect_variant_body_6)
|
||||
|
|
@ -4056,18 +3938,18 @@ circuit check_enum_connect_any:
|
|||
connect o2, _bundle_literal_expr_8 @[module-XXXXXXXXXX.rs 9:1]
|
||||
C:
|
||||
wire __connect_variant_body_7: Ty8 @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire _cast_bits_to_bundle_expr_5: Ty8
|
||||
wire _cast_bits_to_bundle_expr_flattened_5: Ty9
|
||||
connect _cast_bits_to_bundle_expr_flattened_5.tag, bits(bits(i1.body, 0, 0), 0, 0)
|
||||
wire _cast_bits_to_enum_expr_5: Ty3
|
||||
when eq(UInt<1>(0), tail(_cast_bits_to_bundle_expr_flattened_5.tag, 0)):
|
||||
connect _cast_bits_to_enum_expr_5, {|HdlNone, HdlSome|}(HdlNone)
|
||||
wire _cast_bits_to_bundle_expr_3: Ty8
|
||||
wire _cast_bits_to_bundle_expr_flattened_3: Ty9
|
||||
connect _cast_bits_to_bundle_expr_flattened_3.tag, bits(bits(i1.body, 0, 0), 0, 0)
|
||||
wire _cast_bits_to_enum_expr_3: Ty3
|
||||
when eq(UInt<1>(0), tail(_cast_bits_to_bundle_expr_flattened_3.tag, 0)):
|
||||
connect _cast_bits_to_enum_expr_3, {|HdlNone, HdlSome|}(HdlNone)
|
||||
else:
|
||||
connect _cast_bits_to_enum_expr_5, {|HdlNone, HdlSome|}(HdlSome)
|
||||
connect _cast_bits_to_bundle_expr_5.tag, _cast_bits_to_enum_expr_5
|
||||
connect _cast_bits_to_bundle_expr_flattened_5.body, UInt<0>(0)
|
||||
connect _cast_bits_to_bundle_expr_5.body, _cast_bits_to_bundle_expr_flattened_5.body
|
||||
connect __connect_variant_body_7, _cast_bits_to_bundle_expr_5 @[module-XXXXXXXXXX.rs 9:1]
|
||||
connect _cast_bits_to_enum_expr_3, {|HdlNone, HdlSome|}(HdlSome)
|
||||
connect _cast_bits_to_bundle_expr_3.tag, _cast_bits_to_enum_expr_3
|
||||
connect _cast_bits_to_bundle_expr_flattened_3.body, UInt<0>(0)
|
||||
connect _cast_bits_to_bundle_expr_3.body, _cast_bits_to_bundle_expr_flattened_3.body
|
||||
connect __connect_variant_body_7, _cast_bits_to_bundle_expr_3 @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire _bundle_literal_expr_9: Ty2
|
||||
connect _bundle_literal_expr_9.tag, {|A, B, C|}(C)
|
||||
wire _cast_bundle_to_bits_expr_3: Ty9
|
||||
|
|
@ -4134,16 +4016,10 @@ circuit check_enum_connect_any:
|
|||
connect __connect_variant_body_1, _bundle_literal_expr_1 @[module-XXXXXXXXXX.rs 8:1]
|
||||
else:
|
||||
wire __connect_variant_body_2: SInt<1> @[module-XXXXXXXXXX.rs 8:1]
|
||||
wire _cast_bits_to_bundle_expr_1: Ty3
|
||||
wire _cast_bits_to_bundle_expr_flattened_1: Ty3
|
||||
connect _cast_bits_to_bundle_expr_flattened_1.tag, bits(bits(i2.body, 2, 0), 0, 0)
|
||||
connect _cast_bits_to_bundle_expr_1.tag, _cast_bits_to_bundle_expr_flattened_1.tag
|
||||
connect _cast_bits_to_bundle_expr_flattened_1.body, bits(bits(i2.body, 2, 0), 2, 1)
|
||||
connect _cast_bits_to_bundle_expr_1.body, _cast_bits_to_bundle_expr_flattened_1.body
|
||||
; connect different types:
|
||||
; lhs: SInt<1>
|
||||
; rhs: SInt<2>
|
||||
connect __connect_variant_body_2, asSInt(bits(_cast_bits_to_bundle_expr_1.body, 1, 0)) @[module-XXXXXXXXXX.rs 8:1]
|
||||
connect __connect_variant_body_2, asSInt(bits(_cast_bits_to_bundle_expr.body, 1, 0)) @[module-XXXXXXXXXX.rs 8:1]
|
||||
wire _bundle_literal_expr_2: Ty2
|
||||
connect _bundle_literal_expr_2.tag, UInt<1>(0h1)
|
||||
connect _bundle_literal_expr_2.body, asUInt(__connect_variant_body_2)
|
||||
|
|
@ -4159,13 +4035,13 @@ circuit check_enum_connect_any:
|
|||
connect o1, _bundle_literal_expr_3 @[module-XXXXXXXXXX.rs 8:1]
|
||||
else:
|
||||
wire __connect_variant_body_3: Ty4 @[module-XXXXXXXXXX.rs 8:1]
|
||||
wire _cast_bits_to_bundle_expr_2: Ty4
|
||||
wire _cast_bits_to_bundle_expr_flattened_2: Ty4
|
||||
connect _cast_bits_to_bundle_expr_flattened_2.tag, bits(bits(i2.body, 0, 0), 0, 0)
|
||||
connect _cast_bits_to_bundle_expr_2.tag, _cast_bits_to_bundle_expr_flattened_2.tag
|
||||
connect _cast_bits_to_bundle_expr_flattened_2.body, UInt<0>(0)
|
||||
connect _cast_bits_to_bundle_expr_2.body, _cast_bits_to_bundle_expr_flattened_2.body
|
||||
connect __connect_variant_body_3, _cast_bits_to_bundle_expr_2 @[module-XXXXXXXXXX.rs 8:1]
|
||||
wire _cast_bits_to_bundle_expr_1: Ty4
|
||||
wire _cast_bits_to_bundle_expr_flattened_1: Ty4
|
||||
connect _cast_bits_to_bundle_expr_flattened_1.tag, bits(bits(i2.body, 0, 0), 0, 0)
|
||||
connect _cast_bits_to_bundle_expr_1.tag, _cast_bits_to_bundle_expr_flattened_1.tag
|
||||
connect _cast_bits_to_bundle_expr_flattened_1.body, UInt<0>(0)
|
||||
connect _cast_bits_to_bundle_expr_1.body, _cast_bits_to_bundle_expr_flattened_1.body
|
||||
connect __connect_variant_body_3, _cast_bits_to_bundle_expr_1 @[module-XXXXXXXXXX.rs 8:1]
|
||||
wire _bundle_literal_expr_4: Ty0
|
||||
connect _bundle_literal_expr_4.tag, UInt<2>(0h2)
|
||||
wire _cast_bundle_to_bits_expr_1: Ty4
|
||||
|
|
@ -4187,29 +4063,23 @@ circuit check_enum_connect_any:
|
|||
connect o2, _bundle_literal_expr_5 @[module-XXXXXXXXXX.rs 9:1]
|
||||
else when eq(i1.tag, UInt<2>(0h1)): @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire __connect_variant_body_5: Ty3 @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire _cast_bits_to_bundle_expr_3: Ty2
|
||||
wire _cast_bits_to_bundle_expr_flattened_3: Ty2
|
||||
connect _cast_bits_to_bundle_expr_flattened_3.tag, bits(bits(i1.body, 1, 0), 0, 0)
|
||||
connect _cast_bits_to_bundle_expr_3.tag, _cast_bits_to_bundle_expr_flattened_3.tag
|
||||
connect _cast_bits_to_bundle_expr_flattened_3.body, bits(bits(i1.body, 1, 0), 1, 1)
|
||||
connect _cast_bits_to_bundle_expr_3.body, _cast_bits_to_bundle_expr_flattened_3.body
|
||||
when eq(_cast_bits_to_bundle_expr_3.tag, UInt<1>(0h0)): @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire _cast_bits_to_bundle_expr_2: Ty2
|
||||
wire _cast_bits_to_bundle_expr_flattened_2: Ty2
|
||||
connect _cast_bits_to_bundle_expr_flattened_2.tag, bits(bits(i1.body, 1, 0), 0, 0)
|
||||
connect _cast_bits_to_bundle_expr_2.tag, _cast_bits_to_bundle_expr_flattened_2.tag
|
||||
connect _cast_bits_to_bundle_expr_flattened_2.body, bits(bits(i1.body, 1, 0), 1, 1)
|
||||
connect _cast_bits_to_bundle_expr_2.body, _cast_bits_to_bundle_expr_flattened_2.body
|
||||
when eq(_cast_bits_to_bundle_expr_2.tag, UInt<1>(0h0)): @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire _bundle_literal_expr_6: Ty3
|
||||
connect _bundle_literal_expr_6.tag, UInt<1>(0h0)
|
||||
connect _bundle_literal_expr_6.body, UInt<2>(0h0)
|
||||
connect __connect_variant_body_5, _bundle_literal_expr_6 @[module-XXXXXXXXXX.rs 9:1]
|
||||
else:
|
||||
wire __connect_variant_body_6: SInt<2> @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire _cast_bits_to_bundle_expr_4: Ty2
|
||||
wire _cast_bits_to_bundle_expr_flattened_4: Ty2
|
||||
connect _cast_bits_to_bundle_expr_flattened_4.tag, bits(bits(i1.body, 1, 0), 0, 0)
|
||||
connect _cast_bits_to_bundle_expr_4.tag, _cast_bits_to_bundle_expr_flattened_4.tag
|
||||
connect _cast_bits_to_bundle_expr_flattened_4.body, bits(bits(i1.body, 1, 0), 1, 1)
|
||||
connect _cast_bits_to_bundle_expr_4.body, _cast_bits_to_bundle_expr_flattened_4.body
|
||||
; connect different types:
|
||||
; lhs: SInt<2>
|
||||
; rhs: SInt<1>
|
||||
connect __connect_variant_body_6, asSInt(bits(_cast_bits_to_bundle_expr_4.body, 0, 0)) @[module-XXXXXXXXXX.rs 9:1]
|
||||
connect __connect_variant_body_6, asSInt(bits(_cast_bits_to_bundle_expr_2.body, 0, 0)) @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire _bundle_literal_expr_7: Ty3
|
||||
connect _bundle_literal_expr_7.tag, UInt<1>(0h1)
|
||||
connect _bundle_literal_expr_7.body, asUInt(__connect_variant_body_6)
|
||||
|
|
@ -4225,13 +4095,13 @@ circuit check_enum_connect_any:
|
|||
connect o2, _bundle_literal_expr_8 @[module-XXXXXXXXXX.rs 9:1]
|
||||
else:
|
||||
wire __connect_variant_body_7: Ty4 @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire _cast_bits_to_bundle_expr_5: Ty4
|
||||
wire _cast_bits_to_bundle_expr_flattened_5: Ty4
|
||||
connect _cast_bits_to_bundle_expr_flattened_5.tag, bits(bits(i1.body, 0, 0), 0, 0)
|
||||
connect _cast_bits_to_bundle_expr_5.tag, _cast_bits_to_bundle_expr_flattened_5.tag
|
||||
connect _cast_bits_to_bundle_expr_flattened_5.body, UInt<0>(0)
|
||||
connect _cast_bits_to_bundle_expr_5.body, _cast_bits_to_bundle_expr_flattened_5.body
|
||||
connect __connect_variant_body_7, _cast_bits_to_bundle_expr_5 @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire _cast_bits_to_bundle_expr_3: Ty4
|
||||
wire _cast_bits_to_bundle_expr_flattened_3: Ty4
|
||||
connect _cast_bits_to_bundle_expr_flattened_3.tag, bits(bits(i1.body, 0, 0), 0, 0)
|
||||
connect _cast_bits_to_bundle_expr_3.tag, _cast_bits_to_bundle_expr_flattened_3.tag
|
||||
connect _cast_bits_to_bundle_expr_flattened_3.body, UInt<0>(0)
|
||||
connect _cast_bits_to_bundle_expr_3.body, _cast_bits_to_bundle_expr_flattened_3.body
|
||||
connect __connect_variant_body_7, _cast_bits_to_bundle_expr_3 @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire _bundle_literal_expr_9: Ty1
|
||||
connect _bundle_literal_expr_9.tag, UInt<2>(0h2)
|
||||
wire _cast_bundle_to_bits_expr_3: Ty4
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue