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implement simulation of extern modules #26

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programmerjake merged 5 commits from programmerjake/fayalite:sim-extern-module into master 2025-03-26 02:02:54 +00:00
Conversation 0 Commits 5 Files changed 26 +6771 -6962
26 changed files with 6771 additions and 6962 deletions
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1
crates/fayalite/src/firrtl.rs
View file

@ -2258,6 +2258,7 @@ impl<'a> Exporter<'a> {
ModuleBody::Extern(ExternModuleBody { ModuleBody::Extern(ExternModuleBody {
verilog_name, verilog_name,
parameters, parameters,
simulation: _,
}) => { }) => {
let verilog_name = Ident(verilog_name); let verilog_name = Ident(verilog_name);
writeln!(body, "{indent}defname = {verilog_name}").unwrap(); writeln!(body, "{indent}defname = {verilog_name}").unwrap();

6
crates/fayalite/src/int.rs
View file

@ -621,6 +621,12 @@ pub trait BoolOrIntType: Type + sealed::BoolOrIntTypeSealed {
let bitslice = &BitSlice::<u8, Lsb0>::from_slice(&bytes)[..width]; let bitslice = &BitSlice::<u8, Lsb0>::from_slice(&bytes)[..width];
bits.clone_from_bitslice(bitslice); bits.clone_from_bitslice(bitslice);
} }
fn bits_equal_bigint_wrapping(v: &BigInt, bits: &BitSlice) -> bool {
bits.iter()
.by_vals()
.enumerate()
.all(|(bit_index, bit): (usize, bool)| v.bit(bit_index as u64) == bit)
}
fn bits_to_bigint(bits: &BitSlice) -> BigInt { fn bits_to_bigint(bits: &BitSlice) -> BigInt {
let sign_byte = if Self::Signed::VALUE && bits.last().as_deref().copied().unwrap_or(false) { let sign_byte = if Self::Signed::VALUE && bits.last().as_deref().copied().unwrap_or(false) {
0xFF 0xFF

35
crates/fayalite/src/module.rs
View file

@ -21,6 +21,7 @@ use crate::{
memory::{Mem, MemBuilder, MemBuilderTarget, PortName}, memory::{Mem, MemBuilder, MemBuilderTarget, PortName},
reg::Reg, reg::Reg,
reset::{AsyncReset, Reset, ResetType, ResetTypeDispatch, SyncReset}, reset::{AsyncReset, Reset, ResetType, ResetTypeDispatch, SyncReset},
sim::{ExternModuleSimGenerator, ExternModuleSimulation},
source_location::SourceLocation, source_location::SourceLocation,
ty::{CanonicalType, Type}, ty::{CanonicalType, Type},
util::ScopedRef, util::ScopedRef,
@ -33,6 +34,7 @@ use std::{
collections::VecDeque, collections::VecDeque,
convert::Infallible, convert::Infallible,
fmt, fmt,
future::IntoFuture,
hash::{Hash, Hasher}, hash::{Hash, Hasher},
iter::FusedIterator, iter::FusedIterator,
marker::PhantomData, marker::PhantomData,
@ -1081,6 +1083,7 @@ pub struct ExternModuleBody<
> { > {
pub verilog_name: Interned<str>, pub verilog_name: Interned<str>,
pub parameters: P, pub parameters: P,
pub simulation: Option<ExternModuleSimulation>,
} }
impl From<ExternModuleBody<Vec<ExternModuleParameter>>> for ExternModuleBody { impl From<ExternModuleBody<Vec<ExternModuleParameter>>> for ExternModuleBody {
@ -1088,11 +1091,13 @@ impl From<ExternModuleBody<Vec<ExternModuleParameter>>> for ExternModuleBody {
let ExternModuleBody { let ExternModuleBody {
verilog_name, verilog_name,
parameters, parameters,
simulation,
} = value; } = value;
let parameters = Intern::intern_owned(parameters); let parameters = Intern::intern_owned(parameters);
Self { Self {
verilog_name, verilog_name,
parameters, parameters,
simulation,
} }
} }
} }
@ -1283,10 +1288,12 @@ impl<T: BundleType> fmt::Debug for DebugModuleBody<T> {
ModuleBody::Extern(ExternModuleBody { ModuleBody::Extern(ExternModuleBody {
verilog_name, verilog_name,
parameters, parameters,
simulation,
}) => { }) => {
debug_struct debug_struct
.field("verilog_name", verilog_name) .field("verilog_name", verilog_name)
.field("parameters", parameters); .field("parameters", parameters)
.field("simulation", simulation);
} }
} }
debug_struct.finish_non_exhaustive() debug_struct.finish_non_exhaustive()
@ -1761,6 +1768,7 @@ impl AssertValidityState {
ModuleBody::Extern(ExternModuleBody { ModuleBody::Extern(ExternModuleBody {
verilog_name: _, verilog_name: _,
parameters: _, parameters: _,
simulation: _,
}) => {} }) => {}
ModuleBody::Normal(NormalModuleBody { body }) => { ModuleBody::Normal(NormalModuleBody { body }) => {
let body = self.make_block_index(body); let body = self.make_block_index(body);
@ -2108,6 +2116,7 @@ impl ModuleBuilder {
ModuleKind::Extern => ModuleBody::Extern(ExternModuleBody { ModuleKind::Extern => ModuleBody::Extern(ExternModuleBody {
verilog_name: name.0, verilog_name: name.0,
parameters: vec![], parameters: vec![],
simulation: None,
}), }),
ModuleKind::Normal => ModuleBody::Normal(NormalModuleBody { ModuleKind::Normal => ModuleBody::Normal(NormalModuleBody {
body: BuilderModuleBody { body: BuilderModuleBody {
@ -2174,6 +2183,7 @@ impl ModuleBuilder {
.builder_extern_body() .builder_extern_body()
.verilog_name = name.intern(); .verilog_name = name.intern();
} }
#[track_caller]
pub fn parameter(&self, name: impl AsRef<str>, value: ExternModuleParameterValue) { pub fn parameter(&self, name: impl AsRef<str>, value: ExternModuleParameterValue) {
let name = name.as_ref(); let name = name.as_ref();
self.impl_ self.impl_
@ -2186,6 +2196,7 @@ impl ModuleBuilder {
value, value,
}); });
} }
#[track_caller]
pub fn parameter_int(&self, name: impl AsRef<str>, value: impl Into<BigInt>) { pub fn parameter_int(&self, name: impl AsRef<str>, value: impl Into<BigInt>) {
let name = name.as_ref(); let name = name.as_ref();
let value = value.into(); let value = value.into();
@ -2199,6 +2210,7 @@ impl ModuleBuilder {
value: ExternModuleParameterValue::Integer(value), value: ExternModuleParameterValue::Integer(value),
}); });
} }
#[track_caller]
pub fn parameter_str(&self, name: impl AsRef<str>, value: impl AsRef<str>) { pub fn parameter_str(&self, name: impl AsRef<str>, value: impl AsRef<str>) {
let name = name.as_ref(); let name = name.as_ref();
let value = value.as_ref(); let value = value.as_ref();
@ -2212,6 +2224,7 @@ impl ModuleBuilder {
value: ExternModuleParameterValue::String(value.intern()), value: ExternModuleParameterValue::String(value.intern()),
}); });
} }
#[track_caller]
pub fn parameter_raw_verilog(&self, name: impl AsRef<str>, raw_verilog: impl AsRef<str>) { pub fn parameter_raw_verilog(&self, name: impl AsRef<str>, raw_verilog: impl AsRef<str>) {
let name = name.as_ref(); let name = name.as_ref();
let raw_verilog = raw_verilog.as_ref(); let raw_verilog = raw_verilog.as_ref();
@ -2225,6 +2238,26 @@ impl ModuleBuilder {
value: ExternModuleParameterValue::RawVerilog(raw_verilog.intern()), value: ExternModuleParameterValue::RawVerilog(raw_verilog.intern()),
}); });
} }
#[track_caller]
pub fn extern_module_simulation<G: ExternModuleSimGenerator>(&self, generator: G) {
let mut impl_ = self.impl_.borrow_mut();
let simulation = &mut impl_.body.builder_extern_body().simulation;
if simulation.is_some() {
panic!("already added an extern module simulation");
}
*simulation = Some(ExternModuleSimulation::new(generator));
}
#[track_caller]
pub fn extern_module_simulation_fn<
Args: fmt::Debug + Clone + Hash + Eq + Send + Sync + 'static,
Fut: IntoFuture<Output = ()> + 'static,
>(
&self,
args: Args,
f: fn(Args, crate::sim::ExternModuleSimulationState) -> Fut,
) {
self.extern_module_simulation(crate::sim::SimGeneratorFn { args, f });
}
} }
#[track_caller] #[track_caller]

1
crates/fayalite/src/module/transform/visit.rs
View file

@ -31,6 +31,7 @@ use crate::{
phantom_const::PhantomConst, phantom_const::PhantomConst,
reg::Reg, reg::Reg,
reset::{AsyncReset, Reset, ResetType, SyncReset}, reset::{AsyncReset, Reset, ResetType, SyncReset},
sim::ExternModuleSimulation,
source_location::SourceLocation, source_location::SourceLocation,
ty::{CanonicalType, Type}, ty::{CanonicalType, Type},
wire::Wire, wire::Wire,

1707
crates/fayalite/src/sim.rs
View file

File diff suppressed because it is too large Load diff

170
crates/fayalite/tests/sim.rs
View file

@ -3,6 +3,7 @@
use fayalite::{ use fayalite::{
int::UIntValue, int::UIntValue,
module::{instance_with_loc, reg_builder_with_loc},
prelude::*, prelude::*,
reset::ResetType, reset::ResetType,
sim::{time::SimDuration, vcd::VcdWriterDecls, Simulation, ToSimValue}, sim::{time::SimDuration, vcd::VcdWriterDecls, Simulation, ToSimValue},
@ -1443,3 +1444,172 @@ fn test_conditional_assignment_last() {
panic!(); panic!();
} }
} }
#[hdl_module(outline_generated, extern)]
pub fn extern_module() {
#[hdl]
let i: Bool = m.input();
#[hdl]
let o: Bool = m.output();
m.extern_module_simulation_fn((i, o), |(i, o), mut sim| async move {
sim.write(o, true).await;
sim.advance_time(SimDuration::from_nanos(500)).await;
let mut invert = false;
loop {
sim.advance_time(SimDuration::from_micros(1)).await;
let v = sim.read_bool(i).await;
sim.write(o, v ^ invert).await;
invert = !invert;
}
});
}
#[test]
fn test_extern_module() {
let _n = SourceLocation::normalize_files_for_tests();
let mut sim = Simulation::new(extern_module());
let mut writer = RcWriter::default();
sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
sim.write(sim.io().i, false);
sim.advance_time(SimDuration::from_micros(10));
sim.write(sim.io().i, true);
sim.advance_time(SimDuration::from_micros(10));
sim.flush_traces().unwrap();
let vcd = String::from_utf8(writer.take()).unwrap();
println!("####### VCD:\n{vcd}\n#######");
if vcd != include_str!("sim/expected/extern_module.vcd") {
panic!();
}
let sim_debug = format!("{sim:#?}");
println!("#######\n{sim_debug}\n#######");
if sim_debug != include_str!("sim/expected/extern_module.txt") {
panic!();
}
}
#[hdl_module(outline_generated, extern)]
pub fn extern_module2() {
#[hdl]
let en: Bool = m.input();
#[hdl]
let clk: Clock = m.input();
#[hdl]
let o: UInt<8> = m.output();
m.extern_module_simulation_fn((en, clk, o), |(en, clk, o), mut sim| async move {
for b in "Hello, World!\n".bytes().cycle() {
sim.write(o, b).await;
loop {
sim.wait_for_clock_edge(clk).await;
if sim.read_bool(en).await {
break;
}
}
}
});
}
#[test]
fn test_extern_module2() {
let _n = SourceLocation::normalize_files_for_tests();
let mut sim = Simulation::new(extern_module2());
let mut writer = RcWriter::default();
sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
for i in 0..30 {
sim.write(sim.io().en, i % 10 < 5);
sim.write(sim.io().clk, false);
sim.advance_time(SimDuration::from_micros(1));
sim.write(sim.io().clk, true);
sim.advance_time(SimDuration::from_micros(1));
}
sim.flush_traces().unwrap();
let vcd = String::from_utf8(writer.take()).unwrap();
println!("####### VCD:\n{vcd}\n#######");
if vcd != include_str!("sim/expected/extern_module2.vcd") {
panic!();
}
let sim_debug = format!("{sim:#?}");
println!("#######\n{sim_debug}\n#######");
if sim_debug != include_str!("sim/expected/extern_module2.txt") {
panic!();
}
}
// use an extern module to simulate a register to test that the
// simulator can handle chains of alternating circuits and extern modules.
#[hdl_module(outline_generated, extern)]
pub fn sw_reg() {
#[hdl]
let clk: Clock = m.input();
#[hdl]
let o: Bool = m.output();
m.extern_module_simulation_fn((clk, o), |(clk, o), mut sim| async move {
let mut state = false;
loop {
sim.write(o, state).await;
sim.wait_for_clock_edge(clk).await;
state = !state;
}
});
}
#[hdl_module(outline_generated)]
pub fn ripple_counter() {
#[hdl]
let clk: Clock = m.input();
#[hdl]
let o: UInt<6> = m.output();
#[hdl]
let bits: Array<Bool, 6> = wire();
connect_any(o, bits.cast_to_bits());
let mut clk_in = clk;
for (i, bit) in bits.into_iter().enumerate() {
if i % 2 == 0 {
let bit_reg = reg_builder_with_loc(&format!("bit_reg_{i}"), SourceLocation::caller())
.clock_domain(
#[hdl]
ClockDomain {
clk: clk_in,
rst: false.to_sync_reset(),
},
)
.no_reset(Bool)
.build();
connect(bit, bit_reg);
connect(bit_reg, !bit_reg);
} else {
let bit_reg =
instance_with_loc(&format!("bit_reg_{i}"), sw_reg(), SourceLocation::caller());
connect(bit_reg.clk, clk_in);
connect(bit, bit_reg.o);
}
clk_in = bit.to_clock();
}
}
#[test]
fn test_ripple_counter() {
let _n = SourceLocation::normalize_files_for_tests();
let mut sim = Simulation::new(ripple_counter());
let mut writer = RcWriter::default();
sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
for _ in 0..0x80 {
sim.write(sim.io().clk, false);
sim.advance_time(SimDuration::from_micros(1));
sim.write(sim.io().clk, true);
sim.advance_time(SimDuration::from_micros(1));
}
sim.flush_traces().unwrap();
let vcd = String::from_utf8(writer.take()).unwrap();
println!("####### VCD:\n{vcd}\n#######");
if vcd != include_str!("sim/expected/ripple_counter.vcd") {
panic!();
}
let sim_debug = format!("{sim:#?}");
println!("#######\n{sim_debug}\n#######");
if sim_debug != include_str!("sim/expected/ripple_counter.txt") {
panic!();
}
}

1819
crates/fayalite/tests/sim/expected/array_rw.txt
View file

File diff suppressed because it is too large Load diff

57
crates/fayalite/tests/sim/expected/conditional_assignment_last.txt
View file

@ -92,45 +92,30 @@ Simulation {
.. ..
}, },
}, },
uninitialized_inputs: {}, main_module: SimulationModuleState {
io_targets: { base_targets: [
Instance { Instance {
name: <simulator>::conditional_assignment_last, name: <simulator>::conditional_assignment_last,
instantiated: Module { instantiated: Module {
name: conditional_assignment_last, name: conditional_assignment_last,
.. ..
},
}.i: CompiledValue {
layout: CompiledTypeLayout {
ty: Bool,
layout: TypeLayout {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
name: "InstantiatedModule(conditional_assignment_last: conditional_assignment_last).conditional_assignment_last::i",
ty: Bool,
},
],
..
},
}, },
body: Scalar, }.i,
}, ],
range: TypeIndexRange { uninitialized_ios: {},
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 }, io_targets: {
big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 }, Instance {
}, name: <simulator>::conditional_assignment_last,
write: None, instantiated: Module {
name: conditional_assignment_last,
..
},
}.i,
}, },
did_initial_settle: true,
}, },
made_initial_step: true, extern_modules: [],
needs_settle: false, state_ready_to_run: false,
trace_decls: TraceModule { trace_decls: TraceModule {
name: "conditional_assignment_last", name: "conditional_assignment_last",
children: [ children: [

57
crates/fayalite/tests/sim/expected/connect_const.txt
View file

@ -68,45 +68,30 @@ Simulation {
.. ..
}, },
}, },
uninitialized_inputs: {}, main_module: SimulationModuleState {
io_targets: { base_targets: [
Instance { Instance {
name: <simulator>::connect_const, name: <simulator>::connect_const,
instantiated: Module { instantiated: Module {
name: connect_const, name: connect_const,
.. ..
},
}.o: CompiledValue {
layout: CompiledTypeLayout {
ty: UInt<8>,
layout: TypeLayout {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
name: "InstantiatedModule(connect_const: connect_const).connect_const::o",
ty: UInt<8>,
},
],
..
},
}, },
body: Scalar, }.o,
}, ],
range: TypeIndexRange { uninitialized_ios: {},
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 }, io_targets: {
big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 }, Instance {
}, name: <simulator>::connect_const,
write: None, instantiated: Module {
name: connect_const,
..
},
}.o,
}, },
did_initial_settle: true,
}, },
made_initial_step: true, extern_modules: [],
needs_settle: false, state_ready_to_run: false,
trace_decls: TraceModule { trace_decls: TraceModule {
name: "connect_const", name: "connect_const",
children: [ children: [

103
crates/fayalite/tests/sim/expected/connect_const_reset.txt
View file

@ -97,79 +97,44 @@ Simulation {
.. ..
}, },
}, },
uninitialized_inputs: {}, main_module: SimulationModuleState {
io_targets: { base_targets: [
Instance { Instance {
name: <simulator>::connect_const_reset, name: <simulator>::connect_const_reset,
instantiated: Module { instantiated: Module {
name: connect_const_reset, name: connect_const_reset,
.. ..
},
}.bit_out: CompiledValue {
layout: CompiledTypeLayout {
ty: Bool,
layout: TypeLayout {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::bit_out",
ty: Bool,
},
],
..
},
}, },
body: Scalar, }.reset_out,
}, Instance {
range: TypeIndexRange { name: <simulator>::connect_const_reset,
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 }, instantiated: Module {
big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 }, name: connect_const_reset,
}, ..
write: None,
},
Instance {
name: <simulator>::connect_const_reset,
instantiated: Module {
name: connect_const_reset,
..
},
}.reset_out: CompiledValue {
layout: CompiledTypeLayout {
ty: AsyncReset,
layout: TypeLayout {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out",
ty: AsyncReset,
},
],
..
},
}, },
body: Scalar, }.bit_out,
}, ],
range: TypeIndexRange { uninitialized_ios: {},
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 }, io_targets: {
big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 }, Instance {
}, name: <simulator>::connect_const_reset,
write: None, instantiated: Module {
name: connect_const_reset,
..
},
}.bit_out,
Instance {
name: <simulator>::connect_const_reset,
instantiated: Module {
name: connect_const_reset,
..
},
}.reset_out,
}, },
did_initial_settle: true,
}, },
made_initial_step: true, extern_modules: [],
needs_settle: false, state_ready_to_run: false,
trace_decls: TraceModule { trace_decls: TraceModule {
name: "connect_const_reset", name: "connect_const_reset",
children: [ children: [

249
crates/fayalite/tests/sim/expected/counter_async.txt
View file

@ -203,213 +203,58 @@ Simulation {
.. ..
}, },
}, },
uninitialized_inputs: {}, main_module: SimulationModuleState {
io_targets: { base_targets: [
Instance { Instance {
name: <simulator>::counter, name: <simulator>::counter,
instantiated: Module { instantiated: Module {
name: counter, name: counter,
.. ..
},
}.cd: CompiledValue {
layout: CompiledTypeLayout {
ty: Bundle {
/* offset = 0 */
clk: Clock,
/* offset = 1 */
rst: AsyncReset,
}, },
layout: TypeLayout { }.cd,
small_slots: StatePartLayout<SmallSlots> { Instance {
len: 0, name: <simulator>::counter,
debug_data: [], instantiated: Module {
.. name: counter,
}, ..
big_slots: StatePartLayout<BigSlots> {
len: 2,
debug_data: [
SlotDebugData {
name: "InstantiatedModule(counter: counter).counter::cd.clk",
ty: Clock,
},
SlotDebugData {
name: "InstantiatedModule(counter: counter).counter::cd.rst",
ty: AsyncReset,
},
],
..
},
}, },
body: Bundle { }.count,
fields: [ ],
CompiledBundleField { uninitialized_ios: {},
offset: TypeIndex { io_targets: {
small_slots: StatePartIndex<SmallSlots>(0), Instance {
big_slots: StatePartIndex<BigSlots>(0), name: <simulator>::counter,
}, instantiated: Module {
ty: CompiledTypeLayout { name: counter,
ty: Clock, ..
layout: TypeLayout {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
name: "",
ty: Clock,
},
],
..
},
},
body: Scalar,
},
},
CompiledBundleField {
offset: TypeIndex {
small_slots: StatePartIndex<SmallSlots>(0),
big_slots: StatePartIndex<BigSlots>(1),
},
ty: CompiledTypeLayout {
ty: AsyncReset,
layout: TypeLayout {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
name: "",
ty: AsyncReset,
},
],
..
},
},
body: Scalar,
},
},
],
}, },
}, }.cd,
range: TypeIndexRange { Instance {
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 }, name: <simulator>::counter,
big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 2 }, instantiated: Module {
}, name: counter,
write: None, ..
}, },
Instance { }.cd.clk,
name: <simulator>::counter, Instance {
instantiated: Module { name: <simulator>::counter,
name: counter, instantiated: Module {
.. name: counter,
}, ..
}.cd.clk: CompiledValue { },
layout: CompiledTypeLayout { }.cd.rst,
ty: Clock, Instance {
layout: TypeLayout { name: <simulator>::counter,
small_slots: StatePartLayout<SmallSlots> { instantiated: Module {
len: 0, name: counter,
debug_data: [], ..
.. },
}, }.count,
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
name: "",
ty: Clock,
},
],
..
},
},
body: Scalar,
},
range: TypeIndexRange {
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
},
write: None,
},
Instance {
name: <simulator>::counter,
instantiated: Module {
name: counter,
..
},
}.cd.rst: CompiledValue {
layout: CompiledTypeLayout {
ty: AsyncReset,
layout: TypeLayout {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
name: "",
ty: AsyncReset,
},
],
..
},
},
body: Scalar,
},
range: TypeIndexRange {
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
},
write: None,
},
Instance {
name: <simulator>::counter,
instantiated: Module {
name: counter,
..
},
}.count: CompiledValue {
layout: CompiledTypeLayout {
ty: UInt<4>,
layout: TypeLayout {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
name: "InstantiatedModule(counter: counter).counter::count",
ty: UInt<4>,
},
],
..
},
},
body: Scalar,
},
range: TypeIndexRange {
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
big_slots: StatePartIndexRange<BigSlots> { start: 2, len: 1 },
},
write: None,
}, },
did_initial_settle: true,
}, },
made_initial_step: true, extern_modules: [],
needs_settle: false, state_ready_to_run: false,
trace_decls: TraceModule { trace_decls: TraceModule {
name: "counter", name: "counter",
children: [ children: [

249
crates/fayalite/tests/sim/expected/counter_sync.txt
View file

@ -184,213 +184,58 @@ Simulation {
.. ..
}, },
}, },
uninitialized_inputs: {}, main_module: SimulationModuleState {
io_targets: { base_targets: [
Instance { Instance {
name: <simulator>::counter, name: <simulator>::counter,
instantiated: Module { instantiated: Module {
name: counter, name: counter,
.. ..
},
}.cd: CompiledValue {
layout: CompiledTypeLayout {
ty: Bundle {
/* offset = 0 */
clk: Clock,
/* offset = 1 */
rst: SyncReset,
}, },
layout: TypeLayout { }.cd,
small_slots: StatePartLayout<SmallSlots> { Instance {
len: 0, name: <simulator>::counter,
debug_data: [], instantiated: Module {
.. name: counter,
}, ..
big_slots: StatePartLayout<BigSlots> {
len: 2,
debug_data: [
SlotDebugData {
name: "InstantiatedModule(counter: counter).counter::cd.clk",
ty: Clock,
},
SlotDebugData {
name: "InstantiatedModule(counter: counter).counter::cd.rst",
ty: SyncReset,
},
],
..
},
}, },
body: Bundle { }.count,
fields: [ ],
CompiledBundleField { uninitialized_ios: {},
offset: TypeIndex { io_targets: {
small_slots: StatePartIndex<SmallSlots>(0), Instance {
big_slots: StatePartIndex<BigSlots>(0), name: <simulator>::counter,
}, instantiated: Module {
ty: CompiledTypeLayout { name: counter,
ty: Clock, ..
layout: TypeLayout {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
name: "",
ty: Clock,
},
],
..
},
},
body: Scalar,
},
},
CompiledBundleField {
offset: TypeIndex {
small_slots: StatePartIndex<SmallSlots>(0),
big_slots: StatePartIndex<BigSlots>(1),
},
ty: CompiledTypeLayout {
ty: SyncReset,
layout: TypeLayout {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
name: "",
ty: SyncReset,
},
],
..
},
},
body: Scalar,
},
},
],
}, },
}, }.cd,
range: TypeIndexRange { Instance {
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 }, name: <simulator>::counter,
big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 2 }, instantiated: Module {
}, name: counter,
write: None, ..
}, },
Instance { }.cd.clk,
name: <simulator>::counter, Instance {
instantiated: Module { name: <simulator>::counter,
name: counter, instantiated: Module {
.. name: counter,
}, ..
}.cd.clk: CompiledValue { },
layout: CompiledTypeLayout { }.cd.rst,
ty: Clock, Instance {
layout: TypeLayout { name: <simulator>::counter,
small_slots: StatePartLayout<SmallSlots> { instantiated: Module {
len: 0, name: counter,
debug_data: [], ..
.. },
}, }.count,
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
name: "",
ty: Clock,
},
],
..
},
},
body: Scalar,
},
range: TypeIndexRange {
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
},
write: None,
},
Instance {
name: <simulator>::counter,
instantiated: Module {
name: counter,
..
},
}.cd.rst: CompiledValue {
layout: CompiledTypeLayout {
ty: SyncReset,
layout: TypeLayout {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
name: "",
ty: SyncReset,
},
],
..
},
},
body: Scalar,
},
range: TypeIndexRange {
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
},
write: None,
},
Instance {
name: <simulator>::counter,
instantiated: Module {
name: counter,
..
},
}.count: CompiledValue {
layout: CompiledTypeLayout {
ty: UInt<4>,
layout: TypeLayout {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
name: "InstantiatedModule(counter: counter).counter::count",
ty: UInt<4>,
},
],
..
},
},
body: Scalar,
},
range: TypeIndexRange {
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
big_slots: StatePartIndexRange<BigSlots> { start: 2, len: 1 },
},
write: None,
}, },
did_initial_settle: true,
}, },
made_initial_step: true, extern_modules: [],
needs_settle: false, state_ready_to_run: false,
trace_decls: TraceModule { trace_decls: TraceModule {
name: "counter", name: "counter",
children: [ children: [

12
crates/fayalite/tests/sim/expected/duplicate_names.txt
View file

@ -88,10 +88,14 @@ Simulation {
.. ..
}, },
}, },
uninitialized_inputs: {}, main_module: SimulationModuleState {
io_targets: {}, base_targets: [],
made_initial_step: true, uninitialized_ios: {},
needs_settle: false, io_targets: {},
did_initial_settle: true,
},
extern_modules: [],
state_ready_to_run: false,
trace_decls: TraceModule { trace_decls: TraceModule {
name: "duplicate_names", name: "duplicate_names",
children: [ children: [

497
crates/fayalite/tests/sim/expected/enums.txt
View file

@ -1215,389 +1215,128 @@ Simulation {
.. ..
}, },
}, },
uninitialized_inputs: {}, main_module: SimulationModuleState {
io_targets: { base_targets: [
Instance { Instance {
name: <simulator>::enums, name: <simulator>::enums,
instantiated: Module { instantiated: Module {
name: enums, name: enums,
.. ..
},
}.b_out: CompiledValue {
layout: CompiledTypeLayout {
ty: Enum {
HdlNone,
HdlSome(Bundle {0: UInt<1>, 1: Bool}),
}, },
layout: TypeLayout { }.cd,
small_slots: StatePartLayout<SmallSlots> { Instance {
len: 0, name: <simulator>::enums,
debug_data: [], instantiated: Module {
.. name: enums,
}, ..
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
name: "InstantiatedModule(enums: enums).enums::b_out",
ty: Enum {
HdlNone,
HdlSome(Bundle {0: UInt<1>, 1: Bool}),
},
},
],
..
},
}, },
body: Scalar, }.en,
}, Instance {
range: TypeIndexRange { name: <simulator>::enums,
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 }, instantiated: Module {
big_slots: StatePartIndexRange<BigSlots> { start: 7, len: 1 }, name: enums,
}, ..
write: None, },
}, }.which_in,
Instance { Instance {
name: <simulator>::enums, name: <simulator>::enums,
instantiated: Module { instantiated: Module {
name: enums, name: enums,
.. ..
}, },
}.cd: CompiledValue { }.data_in,
layout: CompiledTypeLayout { Instance {
ty: Bundle { name: <simulator>::enums,
/* offset = 0 */ instantiated: Module {
clk: Clock, name: enums,
/* offset = 1 */ ..
rst: SyncReset, },
}, }.which_out,
layout: TypeLayout { Instance {
small_slots: StatePartLayout<SmallSlots> { name: <simulator>::enums,
len: 0, instantiated: Module {
debug_data: [], name: enums,
.. ..
}, },
big_slots: StatePartLayout<BigSlots> { }.data_out,
len: 2, Instance {
debug_data: [ name: <simulator>::enums,
SlotDebugData { instantiated: Module {
name: "InstantiatedModule(enums: enums).enums::cd.clk", name: enums,
ty: Clock, ..
}, },
SlotDebugData { }.b_out,
name: "InstantiatedModule(enums: enums).enums::cd.rst", ],
ty: SyncReset, uninitialized_ios: {},
}, io_targets: {
], Instance {
.. name: <simulator>::enums,
}, instantiated: Module {
}, name: enums,
body: Bundle { ..
fields: [ },
CompiledBundleField { }.b_out,
offset: TypeIndex { Instance {
small_slots: StatePartIndex<SmallSlots>(0), name: <simulator>::enums,
big_slots: StatePartIndex<BigSlots>(0), instantiated: Module {
}, name: enums,
ty: CompiledTypeLayout { ..
ty: Clock, },
layout: TypeLayout { }.cd,
small_slots: StatePartLayout<SmallSlots> { Instance {
len: 0, name: <simulator>::enums,
debug_data: [], instantiated: Module {
.. name: enums,
}, ..
big_slots: StatePartLayout<BigSlots> { },
len: 1, }.cd.clk,
debug_data: [ Instance {
SlotDebugData { name: <simulator>::enums,
name: "", instantiated: Module {
ty: Clock, name: enums,
}, ..
], },
.. }.cd.rst,
}, Instance {
}, name: <simulator>::enums,
body: Scalar, instantiated: Module {
}, name: enums,
}, ..
CompiledBundleField { },
offset: TypeIndex { }.data_in,
small_slots: StatePartIndex<SmallSlots>(0), Instance {
big_slots: StatePartIndex<BigSlots>(1), name: <simulator>::enums,
}, instantiated: Module {
ty: CompiledTypeLayout { name: enums,
ty: SyncReset, ..
layout: TypeLayout { },
small_slots: StatePartLayout<SmallSlots> { }.data_out,
len: 0, Instance {
debug_data: [], name: <simulator>::enums,
.. instantiated: Module {
}, name: enums,
big_slots: StatePartLayout<BigSlots> { ..
len: 1, },
debug_data: [ }.en,
SlotDebugData { Instance {
name: "", name: <simulator>::enums,
ty: SyncReset, instantiated: Module {
}, name: enums,
], ..
.. },
}, }.which_in,
}, Instance {
body: Scalar, name: <simulator>::enums,
}, instantiated: Module {
}, name: enums,
], ..
}, },
}, }.which_out,
range: TypeIndexRange {
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 2 },
},
write: None,
},
Instance {
name: <simulator>::enums,
instantiated: Module {
name: enums,
..
},
}.cd.clk: CompiledValue {
layout: CompiledTypeLayout {
ty: Clock,
layout: TypeLayout {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
name: "",
ty: Clock,
},
],
..
},
},
body: Scalar,
},
range: TypeIndexRange {
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
},
write: None,
},
Instance {
name: <simulator>::enums,
instantiated: Module {
name: enums,
..
},
}.cd.rst: CompiledValue {
layout: CompiledTypeLayout {
ty: SyncReset,
layout: TypeLayout {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
name: "",
ty: SyncReset,
},
],
..
},
},
body: Scalar,
},
range: TypeIndexRange {
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
},
write: None,
},
Instance {
name: <simulator>::enums,
instantiated: Module {
name: enums,
..
},
}.data_in: CompiledValue {
layout: CompiledTypeLayout {
ty: UInt<4>,
layout: TypeLayout {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
name: "InstantiatedModule(enums: enums).enums::data_in",
ty: UInt<4>,
},
],
..
},
},
body: Scalar,
},
range: TypeIndexRange {
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
big_slots: StatePartIndexRange<BigSlots> { start: 4, len: 1 },
},
write: None,
},
Instance {
name: <simulator>::enums,
instantiated: Module {
name: enums,
..
},
}.data_out: CompiledValue {
layout: CompiledTypeLayout {
ty: UInt<4>,
layout: TypeLayout {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
name: "InstantiatedModule(enums: enums).enums::data_out",
ty: UInt<4>,
},
],
..
},
},
body: Scalar,
},
range: TypeIndexRange {
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
big_slots: StatePartIndexRange<BigSlots> { start: 6, len: 1 },
},
write: None,
},
Instance {
name: <simulator>::enums,
instantiated: Module {
name: enums,
..
},
}.en: CompiledValue {
layout: CompiledTypeLayout {
ty: Bool,
layout: TypeLayout {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
name: "InstantiatedModule(enums: enums).enums::en",
ty: Bool,
},
],
..
},
},
body: Scalar,
},
range: TypeIndexRange {
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
big_slots: StatePartIndexRange<BigSlots> { start: 2, len: 1 },
},
write: None,
},
Instance {
name: <simulator>::enums,
instantiated: Module {
name: enums,
..
},
}.which_in: CompiledValue {
layout: CompiledTypeLayout {
ty: UInt<2>,
layout: TypeLayout {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
name: "InstantiatedModule(enums: enums).enums::which_in",
ty: UInt<2>,
},
],
..
},
},
body: Scalar,
},
range: TypeIndexRange {
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
big_slots: StatePartIndexRange<BigSlots> { start: 3, len: 1 },
},
write: None,
},
Instance {
name: <simulator>::enums,
instantiated: Module {
name: enums,
..
},
}.which_out: CompiledValue {
layout: CompiledTypeLayout {
ty: UInt<2>,
layout: TypeLayout {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
name: "InstantiatedModule(enums: enums).enums::which_out",
ty: UInt<2>,
},
],
..
},
},
body: Scalar,
},
range: TypeIndexRange {
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
big_slots: StatePartIndexRange<BigSlots> { start: 5, len: 1 },
},
write: None,
}, },
did_initial_settle: true,
}, },
made_initial_step: true, extern_modules: [],
needs_settle: false, state_ready_to_run: false,
trace_decls: TraceModule { trace_decls: TraceModule {
name: "enums", name: "enums",
children: [ children: [

220
crates/fayalite/tests/sim/expected/extern_module.txt Normal file
View file

@ -0,0 +1,220 @@
Simulation {
state: State {
insns: Insns {
state_layout: StateLayout {
ty: TypeLayout {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartLayout<BigSlots> {
len: 2,
debug_data: [
SlotDebugData {
name: "InstantiatedModule(extern_module: extern_module).extern_module::i",
ty: Bool,
},
SlotDebugData {
name: "InstantiatedModule(extern_module: extern_module).extern_module::o",
ty: Bool,
},
],
..
},
},
memories: StatePartLayout<Memories> {
len: 0,
debug_data: [],
layout_data: [],
..
},
},
insns: [
// at: module-XXXXXXXXXX.rs:1:1
0: Return,
],
..
},
pc: 0,
memory_write_log: [],
memories: StatePart {
value: [],
},
small_slots: StatePart {
value: [],
},
big_slots: StatePart {
value: [
1,
1,
],
},
},
io: Instance {
name: <simulator>::extern_module,
instantiated: Module {
name: extern_module,
..
},
},
main_module: SimulationModuleState {
base_targets: [
Instance {
name: <simulator>::extern_module,
instantiated: Module {
name: extern_module,
..
},
}.i,
Instance {
name: <simulator>::extern_module,
instantiated: Module {
name: extern_module,
..
},
}.o,
],
uninitialized_ios: {},
io_targets: {
Instance {
name: <simulator>::extern_module,
instantiated: Module {
name: extern_module,
..
},
}.i,
Instance {
name: <simulator>::extern_module,
instantiated: Module {
name: extern_module,
..
},
}.o,
},
did_initial_settle: true,
},
extern_modules: [
SimulationExternModuleState {
module_state: SimulationModuleState {
base_targets: [
ModuleIO {
name: extern_module::i,
is_input: true,
ty: Bool,
..
},
ModuleIO {
name: extern_module::o,
is_input: false,
ty: Bool,
..
},
],
uninitialized_ios: {},
io_targets: {
ModuleIO {
name: extern_module::i,
is_input: true,
ty: Bool,
..
},
ModuleIO {
name: extern_module::o,
is_input: false,
ty: Bool,
..
},
},
did_initial_settle: true,
},
sim: ExternModuleSimulation {
generator: SimGeneratorFn {
args: (
ModuleIO {
name: extern_module::i,
is_input: true,
ty: Bool,
..
},
ModuleIO {
name: extern_module::o,
is_input: false,
ty: Bool,
..
},
),
f: ...,
},
source_location: SourceLocation(
module-XXXXXXXXXX.rs:4:1,
),
},
running_generator: Some(
...,
),
wait_targets: {
Instant(
20.500000000000 μs,
),
},
},
],
state_ready_to_run: false,
trace_decls: TraceModule {
name: "extern_module",
children: [
TraceModuleIO {
name: "i",
child: TraceBool {
location: TraceScalarId(0),
name: "i",
flow: Source,
},
ty: Bool,
flow: Source,
},
TraceModuleIO {
name: "o",
child: TraceBool {
location: TraceScalarId(1),
name: "o",
flow: Sink,
},
ty: Bool,
flow: Sink,
},
],
},
traces: [
SimTrace {
id: TraceScalarId(0),
kind: BigBool {
index: StatePartIndex<BigSlots>(0),
},
state: 0x1,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(1),
kind: BigBool {
index: StatePartIndex<BigSlots>(1),
},
state: 0x1,
last_state: 0x1,
},
],
trace_memories: {},
trace_writers: [
Running(
VcdWriter {
finished_init: true,
timescale: 1 ps,
..
},
),
],
instant: 20 μs,
clocks_triggered: [],
..
}

51
crates/fayalite/tests/sim/expected/extern_module.vcd Normal file
View file

@ -0,0 +1,51 @@
$timescale 1 ps $end
$scope module extern_module $end
$var wire 1 ! i $end
$var wire 1 " o $end
$upscope $end
$enddefinitions $end
$dumpvars
0!
1"
$end
#500000
#1500000
0"
#2500000
1"
#3500000
0"
#4500000
1"
#5500000
0"
#6500000
1"
#7500000
0"
#8500000
1"
#9500000
0"
#10000000
1!
#10500000
#11500000
1"
#12500000
0"
#13500000
1"
#14500000
0"
#15500000
1"
#16500000
0"
#17500000
1"
#18500000
0"
#19500000
1"
#20000000

308
crates/fayalite/tests/sim/expected/extern_module2.txt Normal file
View file

@ -0,0 +1,308 @@
Simulation {
state: State {
insns: Insns {
state_layout: StateLayout {
ty: TypeLayout {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartLayout<BigSlots> {
len: 3,
debug_data: [
SlotDebugData {
name: "InstantiatedModule(extern_module2: extern_module2).extern_module2::en",
ty: Bool,
},
SlotDebugData {
name: "InstantiatedModule(extern_module2: extern_module2).extern_module2::clk",
ty: Clock,
},
SlotDebugData {
name: "InstantiatedModule(extern_module2: extern_module2).extern_module2::o",
ty: UInt<8>,
},
],
..
},
},
memories: StatePartLayout<Memories> {
len: 0,
debug_data: [],
layout_data: [],
..
},
},
insns: [
// at: module-XXXXXXXXXX.rs:1:1
0: Return,
],
..
},
pc: 0,
memory_write_log: [],
memories: StatePart {
value: [],
},
small_slots: StatePart {
value: [],
},
big_slots: StatePart {
value: [
0,
1,
101,
],
},
},
io: Instance {
name: <simulator>::extern_module2,
instantiated: Module {
name: extern_module2,
..
},
},
main_module: SimulationModuleState {
base_targets: [
Instance {
name: <simulator>::extern_module2,
instantiated: Module {
name: extern_module2,
..
},
}.en,
Instance {
name: <simulator>::extern_module2,
instantiated: Module {
name: extern_module2,
..
},
}.clk,
Instance {
name: <simulator>::extern_module2,
instantiated: Module {
name: extern_module2,
..
},
}.o,
],
uninitialized_ios: {},
io_targets: {
Instance {
name: <simulator>::extern_module2,
instantiated: Module {
name: extern_module2,
..
},
}.clk,
Instance {
name: <simulator>::extern_module2,
instantiated: Module {
name: extern_module2,
..
},
}.en,
Instance {
name: <simulator>::extern_module2,
instantiated: Module {
name: extern_module2,
..
},
}.o,
},
did_initial_settle: true,
},
extern_modules: [
SimulationExternModuleState {
module_state: SimulationModuleState {
base_targets: [
ModuleIO {
name: extern_module2::en,
is_input: true,
ty: Bool,
..
},
ModuleIO {
name: extern_module2::clk,
is_input: true,
ty: Clock,
..
},
ModuleIO {
name: extern_module2::o,
is_input: false,
ty: UInt<8>,
..
},
],
uninitialized_ios: {},
io_targets: {
ModuleIO {
name: extern_module2::clk,
is_input: true,
ty: Clock,
..
},
ModuleIO {
name: extern_module2::en,
is_input: true,
ty: Bool,
..
},
ModuleIO {
name: extern_module2::o,
is_input: false,
ty: UInt<8>,
..
},
},
did_initial_settle: true,
},
sim: ExternModuleSimulation {
generator: SimGeneratorFn {
args: (
ModuleIO {
name: extern_module2::en,
is_input: true,
ty: Bool,
..
},
ModuleIO {
name: extern_module2::clk,
is_input: true,
ty: Clock,
..
},
ModuleIO {
name: extern_module2::o,
is_input: false,
ty: UInt<8>,
..
},
),
f: ...,
},
source_location: SourceLocation(
module-XXXXXXXXXX.rs:5:1,
),
},
running_generator: Some(
...,
),
wait_targets: {
Change {
key: CompiledValue {
layout: CompiledTypeLayout {
ty: Clock,
layout: TypeLayout {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
name: "InstantiatedModule(extern_module2: extern_module2).extern_module2::clk",
ty: Clock,
},
],
..
},
},
body: Scalar,
},
range: TypeIndexRange {
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
},
write: None,
},
value: SimValue {
ty: Clock,
bits: 0x1,
},
},
},
},
],
state_ready_to_run: false,
trace_decls: TraceModule {
name: "extern_module2",
children: [
TraceModuleIO {
name: "en",
child: TraceBool {
location: TraceScalarId(0),
name: "en",
flow: Source,
},
ty: Bool,
flow: Source,
},
TraceModuleIO {
name: "clk",
child: TraceClock {
location: TraceScalarId(1),
name: "clk",
flow: Source,
},
ty: Clock,
flow: Source,
},
TraceModuleIO {
name: "o",
child: TraceUInt {
location: TraceScalarId(2),
name: "o",
ty: UInt<8>,
flow: Sink,
},
ty: UInt<8>,
flow: Sink,
},
],
},
traces: [
SimTrace {
id: TraceScalarId(0),
kind: BigBool {
index: StatePartIndex<BigSlots>(0),
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(1),
kind: BigClock {
index: StatePartIndex<BigSlots>(1),
},
state: 0x1,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(2),
kind: BigUInt {
index: StatePartIndex<BigSlots>(2),
ty: UInt<8>,
},
state: 0x65,
last_state: 0x65,
},
],
trace_memories: {},
trace_writers: [
Running(
VcdWriter {
finished_init: true,
timescale: 1 ps,
..
},
),
],
instant: 60 μs,
clocks_triggered: [],
..
}

150
crates/fayalite/tests/sim/expected/extern_module2.vcd Normal file
View file

@ -0,0 +1,150 @@
$timescale 1 ps $end
$scope module extern_module2 $end
$var wire 1 ! en $end
$var wire 1 " clk $end
$var wire 8 # o $end
$upscope $end
$enddefinitions $end
$dumpvars
1!
0"
b1001000 #
$end
#1000000
1"
b1100101 #
#2000000
0"
#3000000
1"
b1101100 #
#4000000
0"
#5000000
1"
#6000000
0"
#7000000
1"
b1101111 #
#8000000
0"
#9000000
1"
b101100 #
#10000000
0!
0"
#11000000
1"
#12000000
0"
#13000000
1"
#14000000
0"
#15000000
1"
#16000000
0"
#17000000
1"
#18000000
0"
#19000000
1"
#20000000
1!
0"
#21000000
1"
b100000 #
#22000000
0"
#23000000
1"
b1010111 #
#24000000
0"
#25000000
1"
b1101111 #
#26000000
0"
#27000000
1"
b1110010 #
#28000000
0"
#29000000
1"
b1101100 #
#30000000
0!
0"
#31000000
1"
#32000000
0"
#33000000
1"
#34000000
0"
#35000000
1"
#36000000
0"
#37000000
1"
#38000000
0"
#39000000
1"
#40000000
1!
0"
#41000000
1"
b1100100 #
#42000000
0"
#43000000
1"
b100001 #
#44000000
0"
#45000000
1"
b1010 #
#46000000
0"
#47000000
1"
b1001000 #
#48000000
0"
#49000000
1"
b1100101 #
#50000000
0!
0"
#51000000
1"
#52000000
0"
#53000000
1"
#54000000
0"
#55000000
1"
#56000000
0"
#57000000
1"
#58000000
0"
#59000000
1"
#60000000

1436
crates/fayalite/tests/sim/expected/memories.txt
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File diff suppressed because it is too large Load diff

571
crates/fayalite/tests/sim/expected/memories2.txt
View file

@ -598,514 +598,79 @@ Simulation {
.. ..
}, },
}, },
uninitialized_inputs: {}, main_module: SimulationModuleState {
io_targets: { base_targets: [
Instance { Instance {
name: <simulator>::memories2, name: <simulator>::memories2,
instantiated: Module { instantiated: Module {
name: memories2, name: memories2,
.. ..
},
}.rw: CompiledValue {
layout: CompiledTypeLayout {
ty: Bundle {
/* offset = 0 */
addr: UInt<3>,
/* offset = 3 */
en: Bool,
/* offset = 4 */
clk: Clock,
#[hdl(flip)] /* offset = 5 */
rdata: UInt<2>,
/* offset = 7 */
wmode: Bool,
/* offset = 8 */
wdata: UInt<2>,
/* offset = 10 */
wmask: Bool,
}, },
layout: TypeLayout { }.rw,
small_slots: StatePartLayout<SmallSlots> { ],
len: 0, uninitialized_ios: {},
debug_data: [], io_targets: {
.. Instance {
}, name: <simulator>::memories2,
big_slots: StatePartLayout<BigSlots> { instantiated: Module {
len: 7, name: memories2,
debug_data: [ ..
SlotDebugData {
name: "InstantiatedModule(memories2: memories2).memories2::rw.addr",
ty: UInt<3>,
},
SlotDebugData {
name: "InstantiatedModule(memories2: memories2).memories2::rw.en",
ty: Bool,
},
SlotDebugData {
name: "InstantiatedModule(memories2: memories2).memories2::rw.clk",
ty: Clock,
},
SlotDebugData {
name: "InstantiatedModule(memories2: memories2).memories2::rw.rdata",
ty: UInt<2>,
},
SlotDebugData {
name: "InstantiatedModule(memories2: memories2).memories2::rw.wmode",
ty: Bool,
},
SlotDebugData {
name: "InstantiatedModule(memories2: memories2).memories2::rw.wdata",
ty: UInt<2>,
},
SlotDebugData {
name: "InstantiatedModule(memories2: memories2).memories2::rw.wmask",
ty: Bool,
},
],
..
},
}, },
body: Bundle { }.rw,
fields: [ Instance {
CompiledBundleField { name: <simulator>::memories2,
offset: TypeIndex { instantiated: Module {
small_slots: StatePartIndex<SmallSlots>(0), name: memories2,
big_slots: StatePartIndex<BigSlots>(0), ..
},
ty: CompiledTypeLayout {
ty: UInt<3>,
layout: TypeLayout {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
name: "",
ty: UInt<3>,
},
],
..
},
},
body: Scalar,
},
},
CompiledBundleField {
offset: TypeIndex {
small_slots: StatePartIndex<SmallSlots>(0),
big_slots: StatePartIndex<BigSlots>(1),
},
ty: CompiledTypeLayout {
ty: Bool,
layout: TypeLayout {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
name: "",
ty: Bool,
},
],
..
},
},
body: Scalar,
},
},
CompiledBundleField {
offset: TypeIndex {
small_slots: StatePartIndex<SmallSlots>(0),
big_slots: StatePartIndex<BigSlots>(2),
},
ty: CompiledTypeLayout {
ty: Clock,
layout: TypeLayout {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
name: "",
ty: Clock,
},
],
..
},
},
body: Scalar,
},
},
CompiledBundleField {
offset: TypeIndex {
small_slots: StatePartIndex<SmallSlots>(0),
big_slots: StatePartIndex<BigSlots>(3),
},
ty: CompiledTypeLayout {
ty: UInt<2>,
layout: TypeLayout {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
name: "",
ty: UInt<2>,
},
],
..
},
},
body: Scalar,
},
},
CompiledBundleField {
offset: TypeIndex {
small_slots: StatePartIndex<SmallSlots>(0),
big_slots: StatePartIndex<BigSlots>(4),
},
ty: CompiledTypeLayout {
ty: Bool,
layout: TypeLayout {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
name: "",
ty: Bool,
},
],
..
},
},
body: Scalar,
},
},
CompiledBundleField {
offset: TypeIndex {
small_slots: StatePartIndex<SmallSlots>(0),
big_slots: StatePartIndex<BigSlots>(5),
},
ty: CompiledTypeLayout {
ty: UInt<2>,
layout: TypeLayout {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
name: "",
ty: UInt<2>,
},
],
..
},
},
body: Scalar,
},
},
CompiledBundleField {
offset: TypeIndex {
small_slots: StatePartIndex<SmallSlots>(0),
big_slots: StatePartIndex<BigSlots>(6),
},
ty: CompiledTypeLayout {
ty: Bool,
layout: TypeLayout {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
name: "",
ty: Bool,
},
],
..
},
},
body: Scalar,
},
},
],
}, },
}, }.rw.addr,
range: TypeIndexRange { Instance {
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 }, name: <simulator>::memories2,
big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 7 }, instantiated: Module {
}, name: memories2,
write: None, ..
}, },
Instance { }.rw.clk,
name: <simulator>::memories2, Instance {
instantiated: Module { name: <simulator>::memories2,
name: memories2, instantiated: Module {
.. name: memories2,
}, ..
}.rw.addr: CompiledValue { },
layout: CompiledTypeLayout { }.rw.en,
ty: UInt<3>, Instance {
layout: TypeLayout { name: <simulator>::memories2,
small_slots: StatePartLayout<SmallSlots> { instantiated: Module {
len: 0, name: memories2,
debug_data: [], ..
.. },
}, }.rw.rdata,
big_slots: StatePartLayout<BigSlots> { Instance {
len: 1, name: <simulator>::memories2,
debug_data: [ instantiated: Module {
SlotDebugData { name: memories2,
name: "", ..
ty: UInt<3>, },
}, }.rw.wdata,
], Instance {
.. name: <simulator>::memories2,
}, instantiated: Module {
}, name: memories2,
body: Scalar, ..
}, },
range: TypeIndexRange { }.rw.wmask,
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 }, Instance {
big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 }, name: <simulator>::memories2,
}, instantiated: Module {
write: None, name: memories2,
}, ..
Instance { },
name: <simulator>::memories2, }.rw.wmode,
instantiated: Module {
name: memories2,
..
},
}.rw.clk: CompiledValue {
layout: CompiledTypeLayout {
ty: Clock,
layout: TypeLayout {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
name: "",
ty: Clock,
},
],
..
},
},
body: Scalar,
},
range: TypeIndexRange {
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
big_slots: StatePartIndexRange<BigSlots> { start: 2, len: 1 },
},
write: None,
},
Instance {
name: <simulator>::memories2,
instantiated: Module {
name: memories2,
..
},
}.rw.en: CompiledValue {
layout: CompiledTypeLayout {
ty: Bool,
layout: TypeLayout {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
name: "",
ty: Bool,
},
],
..
},
},
body: Scalar,
},
range: TypeIndexRange {
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
},
write: None,
},
Instance {
name: <simulator>::memories2,
instantiated: Module {
name: memories2,
..
},
}.rw.rdata: CompiledValue {
layout: CompiledTypeLayout {
ty: UInt<2>,
layout: TypeLayout {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
name: "",
ty: UInt<2>,
},
],
..
},
},
body: Scalar,
},
range: TypeIndexRange {
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
big_slots: StatePartIndexRange<BigSlots> { start: 3, len: 1 },
},
write: None,
},
Instance {
name: <simulator>::memories2,
instantiated: Module {
name: memories2,
..
},
}.rw.wdata: CompiledValue {
layout: CompiledTypeLayout {
ty: UInt<2>,
layout: TypeLayout {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
name: "",
ty: UInt<2>,
},
],
..
},
},
body: Scalar,
},
range: TypeIndexRange {
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
big_slots: StatePartIndexRange<BigSlots> { start: 5, len: 1 },
},
write: None,
},
Instance {
name: <simulator>::memories2,
instantiated: Module {
name: memories2,
..
},
}.rw.wmask: CompiledValue {
layout: CompiledTypeLayout {
ty: Bool,
layout: TypeLayout {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
name: "",
ty: Bool,
},
],
..
},
},
body: Scalar,
},
range: TypeIndexRange {
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
big_slots: StatePartIndexRange<BigSlots> { start: 6, len: 1 },
},
write: None,
},
Instance {
name: <simulator>::memories2,
instantiated: Module {
name: memories2,
..
},
}.rw.wmode: CompiledValue {
layout: CompiledTypeLayout {
ty: Bool,
layout: TypeLayout {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
name: "",
ty: Bool,
},
],
..
},
},
body: Scalar,
},
range: TypeIndexRange {
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
big_slots: StatePartIndexRange<BigSlots> { start: 4, len: 1 },
},
write: None,
}, },
did_initial_settle: true,
}, },
made_initial_step: true, extern_modules: [],
needs_settle: false, state_ready_to_run: false,
trace_decls: TraceModule { trace_decls: TraceModule {
name: "memories2", name: "memories2",
children: [ children: [

2135
crates/fayalite/tests/sim/expected/memories3.txt
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File diff suppressed because it is too large Load diff

349
crates/fayalite/tests/sim/expected/mod1.txt
View file

@ -216,313 +216,58 @@ Simulation {
.. ..
}, },
}, },
uninitialized_inputs: {}, main_module: SimulationModuleState {
io_targets: { base_targets: [
Instance { Instance {
name: <simulator>::mod1, name: <simulator>::mod1,
instantiated: Module { instantiated: Module {
name: mod1, name: mod1,
.. ..
},
}.o: CompiledValue {
layout: CompiledTypeLayout {
ty: Bundle {
#[hdl(flip)] /* offset = 0 */
i: UInt<4>,
/* offset = 4 */
o: SInt<2>,
#[hdl(flip)] /* offset = 6 */
i2: SInt<2>,
/* offset = 8 */
o2: UInt<4>,
}, },
layout: TypeLayout { }.o,
small_slots: StatePartLayout<SmallSlots> { ],
len: 0, uninitialized_ios: {},
debug_data: [], io_targets: {
.. Instance {
}, name: <simulator>::mod1,
big_slots: StatePartLayout<BigSlots> { instantiated: Module {
len: 4, name: mod1,
debug_data: [ ..
SlotDebugData {
name: "InstantiatedModule(mod1: mod1).mod1::o.i",
ty: UInt<4>,
},
SlotDebugData {
name: "InstantiatedModule(mod1: mod1).mod1::o.o",
ty: SInt<2>,
},
SlotDebugData {
name: "InstantiatedModule(mod1: mod1).mod1::o.i2",
ty: SInt<2>,
},
SlotDebugData {
name: "InstantiatedModule(mod1: mod1).mod1::o.o2",
ty: UInt<4>,
},
],
..
},
}, },
body: Bundle { }.o,
fields: [ Instance {
CompiledBundleField { name: <simulator>::mod1,
offset: TypeIndex { instantiated: Module {
small_slots: StatePartIndex<SmallSlots>(0), name: mod1,
big_slots: StatePartIndex<BigSlots>(0), ..
},
ty: CompiledTypeLayout {
ty: UInt<4>,
layout: TypeLayout {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
name: "",
ty: UInt<4>,
},
],
..
},
},
body: Scalar,
},
},
CompiledBundleField {
offset: TypeIndex {
small_slots: StatePartIndex<SmallSlots>(0),
big_slots: StatePartIndex<BigSlots>(1),
},
ty: CompiledTypeLayout {
ty: SInt<2>,
layout: TypeLayout {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
name: "",
ty: SInt<2>,
},
],
..
},
},
body: Scalar,
},
},
CompiledBundleField {
offset: TypeIndex {
small_slots: StatePartIndex<SmallSlots>(0),
big_slots: StatePartIndex<BigSlots>(2),
},
ty: CompiledTypeLayout {
ty: SInt<2>,
layout: TypeLayout {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
name: "",
ty: SInt<2>,
},
],
..
},
},
body: Scalar,
},
},
CompiledBundleField {
offset: TypeIndex {
small_slots: StatePartIndex<SmallSlots>(0),
big_slots: StatePartIndex<BigSlots>(3),
},
ty: CompiledTypeLayout {
ty: UInt<4>,
layout: TypeLayout {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
name: "",
ty: UInt<4>,
},
],
..
},
},
body: Scalar,
},
},
],
}, },
}, }.o.i,
range: TypeIndexRange { Instance {
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 }, name: <simulator>::mod1,
big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 4 }, instantiated: Module {
}, name: mod1,
write: None, ..
}, },
Instance { }.o.i2,
name: <simulator>::mod1, Instance {
instantiated: Module { name: <simulator>::mod1,
name: mod1, instantiated: Module {
.. name: mod1,
}, ..
}.o.i: CompiledValue { },
layout: CompiledTypeLayout { }.o.o,
ty: UInt<4>, Instance {
layout: TypeLayout { name: <simulator>::mod1,
small_slots: StatePartLayout<SmallSlots> { instantiated: Module {
len: 0, name: mod1,
debug_data: [], ..
.. },
}, }.o.o2,
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
name: "",
ty: UInt<4>,
},
],
..
},
},
body: Scalar,
},
range: TypeIndexRange {
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
},
write: None,
},
Instance {
name: <simulator>::mod1,
instantiated: Module {
name: mod1,
..
},
}.o.i2: CompiledValue {
layout: CompiledTypeLayout {
ty: SInt<2>,
layout: TypeLayout {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
name: "",
ty: SInt<2>,
},
],
..
},
},
body: Scalar,
},
range: TypeIndexRange {
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
big_slots: StatePartIndexRange<BigSlots> { start: 2, len: 1 },
},
write: None,
},
Instance {
name: <simulator>::mod1,
instantiated: Module {
name: mod1,
..
},
}.o.o: CompiledValue {
layout: CompiledTypeLayout {
ty: SInt<2>,
layout: TypeLayout {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
name: "",
ty: SInt<2>,
},
],
..
},
},
body: Scalar,
},
range: TypeIndexRange {
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
},
write: None,
},
Instance {
name: <simulator>::mod1,
instantiated: Module {
name: mod1,
..
},
}.o.o2: CompiledValue {
layout: CompiledTypeLayout {
ty: UInt<4>,
layout: TypeLayout {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
name: "",
ty: UInt<4>,
},
],
..
},
},
body: Scalar,
},
range: TypeIndexRange {
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
big_slots: StatePartIndexRange<BigSlots> { start: 3, len: 1 },
},
write: None,
}, },
did_initial_settle: true,
}, },
made_initial_step: true, extern_modules: [],
needs_settle: false, state_ready_to_run: false,
trace_decls: TraceModule { trace_decls: TraceModule {
name: "mod1", name: "mod1",
children: [ children: [

1492
crates/fayalite/tests/sim/expected/ripple_counter.txt Normal file
View file

File diff suppressed because it is too large Load diff

1753
crates/fayalite/tests/sim/expected/ripple_counter.vcd Normal file
View file

File diff suppressed because it is too large Load diff

297
crates/fayalite/tests/sim/expected/shift_register.txt
View file

@ -265,247 +265,72 @@ Simulation {
.. ..
}, },
}, },
uninitialized_inputs: {}, main_module: SimulationModuleState {
io_targets: { base_targets: [
Instance { Instance {
name: <simulator>::shift_register, name: <simulator>::shift_register,
instantiated: Module { instantiated: Module {
name: shift_register, name: shift_register,
.. ..
},
}.cd: CompiledValue {
layout: CompiledTypeLayout {
ty: Bundle {
/* offset = 0 */
clk: Clock,
/* offset = 1 */
rst: SyncReset,
}, },
layout: TypeLayout { }.cd,
small_slots: StatePartLayout<SmallSlots> { Instance {
len: 0, name: <simulator>::shift_register,
debug_data: [], instantiated: Module {
.. name: shift_register,
}, ..
big_slots: StatePartLayout<BigSlots> {
len: 2,
debug_data: [
SlotDebugData {
name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.clk",
ty: Clock,
},
SlotDebugData {
name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.rst",
ty: SyncReset,
},
],
..
},
}, },
body: Bundle { }.d,
fields: [ Instance {
CompiledBundleField { name: <simulator>::shift_register,
offset: TypeIndex { instantiated: Module {
small_slots: StatePartIndex<SmallSlots>(0), name: shift_register,
big_slots: StatePartIndex<BigSlots>(0), ..
},
ty: CompiledTypeLayout {
ty: Clock,
layout: TypeLayout {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
name: "",
ty: Clock,
},
],
..
},
},
body: Scalar,
},
},
CompiledBundleField {
offset: TypeIndex {
small_slots: StatePartIndex<SmallSlots>(0),
big_slots: StatePartIndex<BigSlots>(1),
},
ty: CompiledTypeLayout {
ty: SyncReset,
layout: TypeLayout {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
name: "",
ty: SyncReset,
},
],
..
},
},
body: Scalar,
},
},
],
}, },
}, }.q,
range: TypeIndexRange { ],
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 }, uninitialized_ios: {},
big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 2 }, io_targets: {
}, Instance {
write: None, name: <simulator>::shift_register,
}, instantiated: Module {
Instance { name: shift_register,
name: <simulator>::shift_register, ..
instantiated: Module { },
name: shift_register, }.cd,
.. Instance {
}, name: <simulator>::shift_register,
}.cd.clk: CompiledValue { instantiated: Module {
layout: CompiledTypeLayout { name: shift_register,
ty: Clock, ..
layout: TypeLayout { },
small_slots: StatePartLayout<SmallSlots> { }.cd.clk,
len: 0, Instance {
debug_data: [], name: <simulator>::shift_register,
.. instantiated: Module {
}, name: shift_register,
big_slots: StatePartLayout<BigSlots> { ..
len: 1, },
debug_data: [ }.cd.rst,
SlotDebugData { Instance {
name: "", name: <simulator>::shift_register,
ty: Clock, instantiated: Module {
}, name: shift_register,
], ..
.. },
}, }.d,
}, Instance {
body: Scalar, name: <simulator>::shift_register,
}, instantiated: Module {
range: TypeIndexRange { name: shift_register,
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 }, ..
big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 }, },
}, }.q,
write: None,
},
Instance {
name: <simulator>::shift_register,
instantiated: Module {
name: shift_register,
..
},
}.cd.rst: CompiledValue {
layout: CompiledTypeLayout {
ty: SyncReset,
layout: TypeLayout {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
name: "",
ty: SyncReset,
},
],
..
},
},
body: Scalar,
},
range: TypeIndexRange {
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
},
write: None,
},
Instance {
name: <simulator>::shift_register,
instantiated: Module {
name: shift_register,
..
},
}.d: CompiledValue {
layout: CompiledTypeLayout {
ty: Bool,
layout: TypeLayout {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
name: "InstantiatedModule(shift_register: shift_register).shift_register::d",
ty: Bool,
},
],
..
},
},
body: Scalar,
},
range: TypeIndexRange {
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
big_slots: StatePartIndexRange<BigSlots> { start: 2, len: 1 },
},
write: None,
},
Instance {
name: <simulator>::shift_register,
instantiated: Module {
name: shift_register,
..
},
}.q: CompiledValue {
layout: CompiledTypeLayout {
ty: Bool,
layout: TypeLayout {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
name: "InstantiatedModule(shift_register: shift_register).shift_register::q",
ty: Bool,
},
],
..
},
},
body: Scalar,
},
range: TypeIndexRange {
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
big_slots: StatePartIndexRange<BigSlots> { start: 3, len: 1 },
},
write: None,
}, },
did_initial_settle: true,
}, },
made_initial_step: true, extern_modules: [],
needs_settle: false, state_ready_to_run: false,
trace_decls: TraceModule { trace_decls: TraceModule {
name: "shift_register", name: "shift_register",
children: [ children: [

8
crates/fayalite/visit_types.json
View file

@ -160,7 +160,8 @@
"data": { "data": {
"$kind": "Struct", "$kind": "Struct",
"verilog_name": "Visible", "verilog_name": "Visible",
"parameters": "Visible" "parameters": "Visible",
"simulation": "Visible"
} }
}, },
"ExternModuleParameter": { "ExternModuleParameter": {
@ -1269,6 +1270,11 @@
"$kind": "Opaque" "$kind": "Opaque"
}, },
"generics": "<T: ?Sized + crate::phantom_const::PhantomConstValue>" "generics": "<T: ?Sized + crate::phantom_const::PhantomConstValue>"
},
"ExternModuleSimulation": {
"data": {
"$kind": "Opaque"
}
} }
} }
} }