implement simulation of extern modules #26
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@ -2258,6 +2258,7 @@ impl<'a> Exporter<'a> {
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ModuleBody::Extern(ExternModuleBody {
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verilog_name,
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parameters,
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simulation: _,
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}) => {
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let verilog_name = Ident(verilog_name);
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writeln!(body, "{indent}defname = {verilog_name}").unwrap();
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@ -621,6 +621,12 @@ pub trait BoolOrIntType: Type + sealed::BoolOrIntTypeSealed {
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let bitslice = &BitSlice::<u8, Lsb0>::from_slice(&bytes)[..width];
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bits.clone_from_bitslice(bitslice);
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}
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fn bits_equal_bigint_wrapping(v: &BigInt, bits: &BitSlice) -> bool {
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bits.iter()
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.by_vals()
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.enumerate()
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.all(|(bit_index, bit): (usize, bool)| v.bit(bit_index as u64) == bit)
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}
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fn bits_to_bigint(bits: &BitSlice) -> BigInt {
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let sign_byte = if Self::Signed::VALUE && bits.last().as_deref().copied().unwrap_or(false) {
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0xFF
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@ -21,6 +21,7 @@ use crate::{
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memory::{Mem, MemBuilder, MemBuilderTarget, PortName},
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reg::Reg,
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reset::{AsyncReset, Reset, ResetType, ResetTypeDispatch, SyncReset},
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sim::{ExternModuleSimGenerator, ExternModuleSimulation},
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source_location::SourceLocation,
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ty::{CanonicalType, Type},
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util::ScopedRef,
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@ -33,6 +34,7 @@ use std::{
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collections::VecDeque,
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convert::Infallible,
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fmt,
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future::IntoFuture,
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hash::{Hash, Hasher},
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iter::FusedIterator,
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marker::PhantomData,
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@ -1081,6 +1083,7 @@ pub struct ExternModuleBody<
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> {
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pub verilog_name: Interned<str>,
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pub parameters: P,
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pub simulation: Option<ExternModuleSimulation>,
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}
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impl From<ExternModuleBody<Vec<ExternModuleParameter>>> for ExternModuleBody {
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@ -1088,11 +1091,13 @@ impl From<ExternModuleBody<Vec<ExternModuleParameter>>> for ExternModuleBody {
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let ExternModuleBody {
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verilog_name,
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parameters,
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simulation,
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} = value;
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let parameters = Intern::intern_owned(parameters);
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Self {
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verilog_name,
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parameters,
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simulation,
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}
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}
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}
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@ -1283,10 +1288,12 @@ impl<T: BundleType> fmt::Debug for DebugModuleBody<T> {
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ModuleBody::Extern(ExternModuleBody {
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verilog_name,
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parameters,
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simulation,
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}) => {
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debug_struct
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.field("verilog_name", verilog_name)
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.field("parameters", parameters);
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.field("parameters", parameters)
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.field("simulation", simulation);
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}
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}
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debug_struct.finish_non_exhaustive()
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@ -1761,6 +1768,7 @@ impl AssertValidityState {
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ModuleBody::Extern(ExternModuleBody {
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verilog_name: _,
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parameters: _,
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simulation: _,
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}) => {}
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ModuleBody::Normal(NormalModuleBody { body }) => {
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let body = self.make_block_index(body);
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@ -2108,6 +2116,7 @@ impl ModuleBuilder {
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ModuleKind::Extern => ModuleBody::Extern(ExternModuleBody {
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verilog_name: name.0,
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parameters: vec![],
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simulation: None,
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}),
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ModuleKind::Normal => ModuleBody::Normal(NormalModuleBody {
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body: BuilderModuleBody {
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@ -2174,6 +2183,7 @@ impl ModuleBuilder {
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.builder_extern_body()
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.verilog_name = name.intern();
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}
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#[track_caller]
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pub fn parameter(&self, name: impl AsRef<str>, value: ExternModuleParameterValue) {
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let name = name.as_ref();
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self.impl_
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@ -2186,6 +2196,7 @@ impl ModuleBuilder {
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value,
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});
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}
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#[track_caller]
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pub fn parameter_int(&self, name: impl AsRef<str>, value: impl Into<BigInt>) {
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let name = name.as_ref();
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let value = value.into();
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@ -2199,6 +2210,7 @@ impl ModuleBuilder {
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value: ExternModuleParameterValue::Integer(value),
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});
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}
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#[track_caller]
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pub fn parameter_str(&self, name: impl AsRef<str>, value: impl AsRef<str>) {
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let name = name.as_ref();
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let value = value.as_ref();
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@ -2212,6 +2224,7 @@ impl ModuleBuilder {
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value: ExternModuleParameterValue::String(value.intern()),
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});
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}
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#[track_caller]
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pub fn parameter_raw_verilog(&self, name: impl AsRef<str>, raw_verilog: impl AsRef<str>) {
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let name = name.as_ref();
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let raw_verilog = raw_verilog.as_ref();
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@ -2225,6 +2238,26 @@ impl ModuleBuilder {
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value: ExternModuleParameterValue::RawVerilog(raw_verilog.intern()),
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});
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}
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#[track_caller]
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pub fn extern_module_simulation<G: ExternModuleSimGenerator>(&self, generator: G) {
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let mut impl_ = self.impl_.borrow_mut();
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let simulation = &mut impl_.body.builder_extern_body().simulation;
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if simulation.is_some() {
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panic!("already added an extern module simulation");
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}
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*simulation = Some(ExternModuleSimulation::new(generator));
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}
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#[track_caller]
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pub fn extern_module_simulation_fn<
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Args: fmt::Debug + Clone + Hash + Eq + Send + Sync + 'static,
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Fut: IntoFuture<Output = ()> + 'static,
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>(
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&self,
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args: Args,
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f: fn(Args, crate::sim::ExternModuleSimulationState) -> Fut,
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) {
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self.extern_module_simulation(crate::sim::SimGeneratorFn { args, f });
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}
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}
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#[track_caller]
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@ -31,6 +31,7 @@ use crate::{
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phantom_const::PhantomConst,
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reg::Reg,
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reset::{AsyncReset, Reset, ResetType, SyncReset},
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sim::ExternModuleSimulation,
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source_location::SourceLocation,
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ty::{CanonicalType, Type},
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wire::Wire,
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File diff suppressed because it is too large
Load diff
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@ -3,6 +3,7 @@
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use fayalite::{
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int::UIntValue,
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module::{instance_with_loc, reg_builder_with_loc},
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prelude::*,
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reset::ResetType,
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sim::{time::SimDuration, vcd::VcdWriterDecls, Simulation, ToSimValue},
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@ -1443,3 +1444,172 @@ fn test_conditional_assignment_last() {
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panic!();
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}
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}
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#[hdl_module(outline_generated, extern)]
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pub fn extern_module() {
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#[hdl]
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let i: Bool = m.input();
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#[hdl]
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let o: Bool = m.output();
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m.extern_module_simulation_fn((i, o), |(i, o), mut sim| async move {
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sim.write(o, true).await;
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sim.advance_time(SimDuration::from_nanos(500)).await;
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let mut invert = false;
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loop {
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sim.advance_time(SimDuration::from_micros(1)).await;
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let v = sim.read_bool(i).await;
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sim.write(o, v ^ invert).await;
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invert = !invert;
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}
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});
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}
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#[test]
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fn test_extern_module() {
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let _n = SourceLocation::normalize_files_for_tests();
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let mut sim = Simulation::new(extern_module());
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let mut writer = RcWriter::default();
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sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
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sim.write(sim.io().i, false);
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sim.advance_time(SimDuration::from_micros(10));
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sim.write(sim.io().i, true);
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sim.advance_time(SimDuration::from_micros(10));
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sim.flush_traces().unwrap();
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let vcd = String::from_utf8(writer.take()).unwrap();
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println!("####### VCD:\n{vcd}\n#######");
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if vcd != include_str!("sim/expected/extern_module.vcd") {
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panic!();
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}
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let sim_debug = format!("{sim:#?}");
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println!("#######\n{sim_debug}\n#######");
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if sim_debug != include_str!("sim/expected/extern_module.txt") {
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panic!();
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}
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}
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#[hdl_module(outline_generated, extern)]
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pub fn extern_module2() {
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#[hdl]
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let en: Bool = m.input();
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#[hdl]
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let clk: Clock = m.input();
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#[hdl]
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let o: UInt<8> = m.output();
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m.extern_module_simulation_fn((en, clk, o), |(en, clk, o), mut sim| async move {
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for b in "Hello, World!\n".bytes().cycle() {
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sim.write(o, b).await;
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loop {
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sim.wait_for_clock_edge(clk).await;
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if sim.read_bool(en).await {
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break;
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}
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}
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}
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});
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}
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#[test]
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fn test_extern_module2() {
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let _n = SourceLocation::normalize_files_for_tests();
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let mut sim = Simulation::new(extern_module2());
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let mut writer = RcWriter::default();
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sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
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for i in 0..30 {
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sim.write(sim.io().en, i % 10 < 5);
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sim.write(sim.io().clk, false);
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sim.advance_time(SimDuration::from_micros(1));
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sim.write(sim.io().clk, true);
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sim.advance_time(SimDuration::from_micros(1));
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}
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sim.flush_traces().unwrap();
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let vcd = String::from_utf8(writer.take()).unwrap();
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println!("####### VCD:\n{vcd}\n#######");
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if vcd != include_str!("sim/expected/extern_module2.vcd") {
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panic!();
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}
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let sim_debug = format!("{sim:#?}");
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println!("#######\n{sim_debug}\n#######");
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if sim_debug != include_str!("sim/expected/extern_module2.txt") {
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panic!();
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}
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}
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// use an extern module to simulate a register to test that the
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// simulator can handle chains of alternating circuits and extern modules.
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#[hdl_module(outline_generated, extern)]
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pub fn sw_reg() {
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#[hdl]
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let clk: Clock = m.input();
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#[hdl]
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let o: Bool = m.output();
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m.extern_module_simulation_fn((clk, o), |(clk, o), mut sim| async move {
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let mut state = false;
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loop {
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sim.write(o, state).await;
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sim.wait_for_clock_edge(clk).await;
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state = !state;
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}
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});
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}
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#[hdl_module(outline_generated)]
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pub fn ripple_counter() {
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#[hdl]
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let clk: Clock = m.input();
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#[hdl]
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let o: UInt<6> = m.output();
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#[hdl]
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let bits: Array<Bool, 6> = wire();
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connect_any(o, bits.cast_to_bits());
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let mut clk_in = clk;
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for (i, bit) in bits.into_iter().enumerate() {
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if i % 2 == 0 {
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let bit_reg = reg_builder_with_loc(&format!("bit_reg_{i}"), SourceLocation::caller())
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.clock_domain(
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#[hdl]
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ClockDomain {
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clk: clk_in,
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rst: false.to_sync_reset(),
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},
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)
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.no_reset(Bool)
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.build();
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connect(bit, bit_reg);
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connect(bit_reg, !bit_reg);
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} else {
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let bit_reg =
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instance_with_loc(&format!("bit_reg_{i}"), sw_reg(), SourceLocation::caller());
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connect(bit_reg.clk, clk_in);
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connect(bit, bit_reg.o);
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}
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clk_in = bit.to_clock();
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}
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}
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#[test]
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fn test_ripple_counter() {
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let _n = SourceLocation::normalize_files_for_tests();
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let mut sim = Simulation::new(ripple_counter());
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let mut writer = RcWriter::default();
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sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
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for _ in 0..0x80 {
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sim.write(sim.io().clk, false);
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sim.advance_time(SimDuration::from_micros(1));
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sim.write(sim.io().clk, true);
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sim.advance_time(SimDuration::from_micros(1));
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}
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sim.flush_traces().unwrap();
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let vcd = String::from_utf8(writer.take()).unwrap();
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println!("####### VCD:\n{vcd}\n#######");
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if vcd != include_str!("sim/expected/ripple_counter.vcd") {
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panic!();
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}
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let sim_debug = format!("{sim:#?}");
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println!("#######\n{sim_debug}\n#######");
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if sim_debug != include_str!("sim/expected/ripple_counter.txt") {
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panic!();
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}
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}
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File diff suppressed because it is too large
Load diff
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@ -92,45 +92,30 @@ Simulation {
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..
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},
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},
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uninitialized_inputs: {},
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io_targets: {
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Instance {
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name: <simulator>::conditional_assignment_last,
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instantiated: Module {
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name: conditional_assignment_last,
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..
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},
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}.i: CompiledValue {
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layout: CompiledTypeLayout {
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ty: Bool,
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layout: TypeLayout {
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small_slots: StatePartLayout<SmallSlots> {
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len: 0,
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debug_data: [],
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..
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},
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big_slots: StatePartLayout<BigSlots> {
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len: 1,
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debug_data: [
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SlotDebugData {
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name: "InstantiatedModule(conditional_assignment_last: conditional_assignment_last).conditional_assignment_last::i",
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ty: Bool,
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},
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],
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..
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},
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main_module: SimulationModuleState {
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base_targets: [
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Instance {
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name: <simulator>::conditional_assignment_last,
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instantiated: Module {
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name: conditional_assignment_last,
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..
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},
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body: Scalar,
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},
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range: TypeIndexRange {
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small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
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big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
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},
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write: None,
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}.i,
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],
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uninitialized_ios: {},
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io_targets: {
|
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Instance {
|
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name: <simulator>::conditional_assignment_last,
|
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instantiated: Module {
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name: conditional_assignment_last,
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..
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},
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}.i,
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},
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did_initial_settle: true,
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},
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made_initial_step: true,
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needs_settle: false,
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extern_modules: [],
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state_ready_to_run: false,
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trace_decls: TraceModule {
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name: "conditional_assignment_last",
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children: [
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|
|
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|
|
@ -68,45 +68,30 @@ Simulation {
|
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..
|
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},
|
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},
|
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uninitialized_inputs: {},
|
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io_targets: {
|
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Instance {
|
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name: <simulator>::connect_const,
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instantiated: Module {
|
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name: connect_const,
|
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..
|
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},
|
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}.o: CompiledValue {
|
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layout: CompiledTypeLayout {
|
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ty: UInt<8>,
|
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layout: TypeLayout {
|
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small_slots: StatePartLayout<SmallSlots> {
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len: 0,
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debug_data: [],
|
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..
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},
|
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big_slots: StatePartLayout<BigSlots> {
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len: 1,
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debug_data: [
|
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SlotDebugData {
|
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name: "InstantiatedModule(connect_const: connect_const).connect_const::o",
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ty: UInt<8>,
|
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},
|
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],
|
||||
..
|
||||
},
|
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main_module: SimulationModuleState {
|
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base_targets: [
|
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Instance {
|
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name: <simulator>::connect_const,
|
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instantiated: Module {
|
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name: connect_const,
|
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..
|
||||
},
|
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body: Scalar,
|
||||
},
|
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range: TypeIndexRange {
|
||||
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
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big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
|
||||
},
|
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write: None,
|
||||
}.o,
|
||||
],
|
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uninitialized_ios: {},
|
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io_targets: {
|
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Instance {
|
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name: <simulator>::connect_const,
|
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instantiated: Module {
|
||||
name: connect_const,
|
||||
..
|
||||
},
|
||||
}.o,
|
||||
},
|
||||
did_initial_settle: true,
|
||||
},
|
||||
made_initial_step: true,
|
||||
needs_settle: false,
|
||||
extern_modules: [],
|
||||
state_ready_to_run: false,
|
||||
trace_decls: TraceModule {
|
||||
name: "connect_const",
|
||||
children: [
|
||||
|
|
|
|||
|
|
@ -97,79 +97,44 @@ Simulation {
|
|||
..
|
||||
},
|
||||
},
|
||||
uninitialized_inputs: {},
|
||||
io_targets: {
|
||||
Instance {
|
||||
name: <simulator>::connect_const_reset,
|
||||
instantiated: Module {
|
||||
name: connect_const_reset,
|
||||
..
|
||||
},
|
||||
}.bit_out: CompiledValue {
|
||||
layout: CompiledTypeLayout {
|
||||
ty: Bool,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::bit_out",
|
||||
ty: Bool,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
main_module: SimulationModuleState {
|
||||
base_targets: [
|
||||
Instance {
|
||||
name: <simulator>::connect_const_reset,
|
||||
instantiated: Module {
|
||||
name: connect_const_reset,
|
||||
..
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
|
||||
},
|
||||
write: None,
|
||||
},
|
||||
Instance {
|
||||
name: <simulator>::connect_const_reset,
|
||||
instantiated: Module {
|
||||
name: connect_const_reset,
|
||||
..
|
||||
},
|
||||
}.reset_out: CompiledValue {
|
||||
layout: CompiledTypeLayout {
|
||||
ty: AsyncReset,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out",
|
||||
ty: AsyncReset,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
}.reset_out,
|
||||
Instance {
|
||||
name: <simulator>::connect_const_reset,
|
||||
instantiated: Module {
|
||||
name: connect_const_reset,
|
||||
..
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
|
||||
},
|
||||
write: None,
|
||||
}.bit_out,
|
||||
],
|
||||
uninitialized_ios: {},
|
||||
io_targets: {
|
||||
Instance {
|
||||
name: <simulator>::connect_const_reset,
|
||||
instantiated: Module {
|
||||
name: connect_const_reset,
|
||||
..
|
||||
},
|
||||
}.bit_out,
|
||||
Instance {
|
||||
name: <simulator>::connect_const_reset,
|
||||
instantiated: Module {
|
||||
name: connect_const_reset,
|
||||
..
|
||||
},
|
||||
}.reset_out,
|
||||
},
|
||||
did_initial_settle: true,
|
||||
},
|
||||
made_initial_step: true,
|
||||
needs_settle: false,
|
||||
extern_modules: [],
|
||||
state_ready_to_run: false,
|
||||
trace_decls: TraceModule {
|
||||
name: "connect_const_reset",
|
||||
children: [
|
||||
|
|
|
|||
|
|
@ -203,213 +203,58 @@ Simulation {
|
|||
..
|
||||
},
|
||||
},
|
||||
uninitialized_inputs: {},
|
||||
io_targets: {
|
||||
Instance {
|
||||
name: <simulator>::counter,
|
||||
instantiated: Module {
|
||||
name: counter,
|
||||
..
|
||||
},
|
||||
}.cd: CompiledValue {
|
||||
layout: CompiledTypeLayout {
|
||||
ty: Bundle {
|
||||
/* offset = 0 */
|
||||
clk: Clock,
|
||||
/* offset = 1 */
|
||||
rst: AsyncReset,
|
||||
main_module: SimulationModuleState {
|
||||
base_targets: [
|
||||
Instance {
|
||||
name: <simulator>::counter,
|
||||
instantiated: Module {
|
||||
name: counter,
|
||||
..
|
||||
},
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartLayout<BigSlots> {
|
||||
len: 2,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(counter: counter).counter::cd.clk",
|
||||
ty: Clock,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(counter: counter).counter::cd.rst",
|
||||
ty: AsyncReset,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
}.cd,
|
||||
Instance {
|
||||
name: <simulator>::counter,
|
||||
instantiated: Module {
|
||||
name: counter,
|
||||
..
|
||||
},
|
||||
body: Bundle {
|
||||
fields: [
|
||||
CompiledBundleField {
|
||||
offset: TypeIndex {
|
||||
small_slots: StatePartIndex<SmallSlots>(0),
|
||||
big_slots: StatePartIndex<BigSlots>(0),
|
||||
},
|
||||
ty: CompiledTypeLayout {
|
||||
ty: Clock,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: Clock,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
},
|
||||
CompiledBundleField {
|
||||
offset: TypeIndex {
|
||||
small_slots: StatePartIndex<SmallSlots>(0),
|
||||
big_slots: StatePartIndex<BigSlots>(1),
|
||||
},
|
||||
ty: CompiledTypeLayout {
|
||||
ty: AsyncReset,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: AsyncReset,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
},
|
||||
],
|
||||
}.count,
|
||||
],
|
||||
uninitialized_ios: {},
|
||||
io_targets: {
|
||||
Instance {
|
||||
name: <simulator>::counter,
|
||||
instantiated: Module {
|
||||
name: counter,
|
||||
..
|
||||
},
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 2 },
|
||||
},
|
||||
write: None,
|
||||
},
|
||||
Instance {
|
||||
name: <simulator>::counter,
|
||||
instantiated: Module {
|
||||
name: counter,
|
||||
..
|
||||
},
|
||||
}.cd.clk: CompiledValue {
|
||||
layout: CompiledTypeLayout {
|
||||
ty: Clock,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: Clock,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
|
||||
},
|
||||
write: None,
|
||||
},
|
||||
Instance {
|
||||
name: <simulator>::counter,
|
||||
instantiated: Module {
|
||||
name: counter,
|
||||
..
|
||||
},
|
||||
}.cd.rst: CompiledValue {
|
||||
layout: CompiledTypeLayout {
|
||||
ty: AsyncReset,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: AsyncReset,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
|
||||
},
|
||||
write: None,
|
||||
},
|
||||
Instance {
|
||||
name: <simulator>::counter,
|
||||
instantiated: Module {
|
||||
name: counter,
|
||||
..
|
||||
},
|
||||
}.count: CompiledValue {
|
||||
layout: CompiledTypeLayout {
|
||||
ty: UInt<4>,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(counter: counter).counter::count",
|
||||
ty: UInt<4>,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 2, len: 1 },
|
||||
},
|
||||
write: None,
|
||||
}.cd,
|
||||
Instance {
|
||||
name: <simulator>::counter,
|
||||
instantiated: Module {
|
||||
name: counter,
|
||||
..
|
||||
},
|
||||
}.cd.clk,
|
||||
Instance {
|
||||
name: <simulator>::counter,
|
||||
instantiated: Module {
|
||||
name: counter,
|
||||
..
|
||||
},
|
||||
}.cd.rst,
|
||||
Instance {
|
||||
name: <simulator>::counter,
|
||||
instantiated: Module {
|
||||
name: counter,
|
||||
..
|
||||
},
|
||||
}.count,
|
||||
},
|
||||
did_initial_settle: true,
|
||||
},
|
||||
made_initial_step: true,
|
||||
needs_settle: false,
|
||||
extern_modules: [],
|
||||
state_ready_to_run: false,
|
||||
trace_decls: TraceModule {
|
||||
name: "counter",
|
||||
children: [
|
||||
|
|
|
|||
|
|
@ -184,213 +184,58 @@ Simulation {
|
|||
..
|
||||
},
|
||||
},
|
||||
uninitialized_inputs: {},
|
||||
io_targets: {
|
||||
Instance {
|
||||
name: <simulator>::counter,
|
||||
instantiated: Module {
|
||||
name: counter,
|
||||
..
|
||||
},
|
||||
}.cd: CompiledValue {
|
||||
layout: CompiledTypeLayout {
|
||||
ty: Bundle {
|
||||
/* offset = 0 */
|
||||
clk: Clock,
|
||||
/* offset = 1 */
|
||||
rst: SyncReset,
|
||||
main_module: SimulationModuleState {
|
||||
base_targets: [
|
||||
Instance {
|
||||
name: <simulator>::counter,
|
||||
instantiated: Module {
|
||||
name: counter,
|
||||
..
|
||||
},
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartLayout<BigSlots> {
|
||||
len: 2,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(counter: counter).counter::cd.clk",
|
||||
ty: Clock,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(counter: counter).counter::cd.rst",
|
||||
ty: SyncReset,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
}.cd,
|
||||
Instance {
|
||||
name: <simulator>::counter,
|
||||
instantiated: Module {
|
||||
name: counter,
|
||||
..
|
||||
},
|
||||
body: Bundle {
|
||||
fields: [
|
||||
CompiledBundleField {
|
||||
offset: TypeIndex {
|
||||
small_slots: StatePartIndex<SmallSlots>(0),
|
||||
big_slots: StatePartIndex<BigSlots>(0),
|
||||
},
|
||||
ty: CompiledTypeLayout {
|
||||
ty: Clock,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: Clock,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
},
|
||||
CompiledBundleField {
|
||||
offset: TypeIndex {
|
||||
small_slots: StatePartIndex<SmallSlots>(0),
|
||||
big_slots: StatePartIndex<BigSlots>(1),
|
||||
},
|
||||
ty: CompiledTypeLayout {
|
||||
ty: SyncReset,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: SyncReset,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
},
|
||||
],
|
||||
}.count,
|
||||
],
|
||||
uninitialized_ios: {},
|
||||
io_targets: {
|
||||
Instance {
|
||||
name: <simulator>::counter,
|
||||
instantiated: Module {
|
||||
name: counter,
|
||||
..
|
||||
},
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 2 },
|
||||
},
|
||||
write: None,
|
||||
},
|
||||
Instance {
|
||||
name: <simulator>::counter,
|
||||
instantiated: Module {
|
||||
name: counter,
|
||||
..
|
||||
},
|
||||
}.cd.clk: CompiledValue {
|
||||
layout: CompiledTypeLayout {
|
||||
ty: Clock,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: Clock,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
|
||||
},
|
||||
write: None,
|
||||
},
|
||||
Instance {
|
||||
name: <simulator>::counter,
|
||||
instantiated: Module {
|
||||
name: counter,
|
||||
..
|
||||
},
|
||||
}.cd.rst: CompiledValue {
|
||||
layout: CompiledTypeLayout {
|
||||
ty: SyncReset,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: SyncReset,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
|
||||
},
|
||||
write: None,
|
||||
},
|
||||
Instance {
|
||||
name: <simulator>::counter,
|
||||
instantiated: Module {
|
||||
name: counter,
|
||||
..
|
||||
},
|
||||
}.count: CompiledValue {
|
||||
layout: CompiledTypeLayout {
|
||||
ty: UInt<4>,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(counter: counter).counter::count",
|
||||
ty: UInt<4>,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 2, len: 1 },
|
||||
},
|
||||
write: None,
|
||||
}.cd,
|
||||
Instance {
|
||||
name: <simulator>::counter,
|
||||
instantiated: Module {
|
||||
name: counter,
|
||||
..
|
||||
},
|
||||
}.cd.clk,
|
||||
Instance {
|
||||
name: <simulator>::counter,
|
||||
instantiated: Module {
|
||||
name: counter,
|
||||
..
|
||||
},
|
||||
}.cd.rst,
|
||||
Instance {
|
||||
name: <simulator>::counter,
|
||||
instantiated: Module {
|
||||
name: counter,
|
||||
..
|
||||
},
|
||||
}.count,
|
||||
},
|
||||
did_initial_settle: true,
|
||||
},
|
||||
made_initial_step: true,
|
||||
needs_settle: false,
|
||||
extern_modules: [],
|
||||
state_ready_to_run: false,
|
||||
trace_decls: TraceModule {
|
||||
name: "counter",
|
||||
children: [
|
||||
|
|
|
|||
|
|
@ -88,10 +88,14 @@ Simulation {
|
|||
..
|
||||
},
|
||||
},
|
||||
uninitialized_inputs: {},
|
||||
io_targets: {},
|
||||
made_initial_step: true,
|
||||
needs_settle: false,
|
||||
main_module: SimulationModuleState {
|
||||
base_targets: [],
|
||||
uninitialized_ios: {},
|
||||
io_targets: {},
|
||||
did_initial_settle: true,
|
||||
},
|
||||
extern_modules: [],
|
||||
state_ready_to_run: false,
|
||||
trace_decls: TraceModule {
|
||||
name: "duplicate_names",
|
||||
children: [
|
||||
|
|
|
|||
|
|
@ -1215,389 +1215,128 @@ Simulation {
|
|||
..
|
||||
},
|
||||
},
|
||||
uninitialized_inputs: {},
|
||||
io_targets: {
|
||||
Instance {
|
||||
name: <simulator>::enums,
|
||||
instantiated: Module {
|
||||
name: enums,
|
||||
..
|
||||
},
|
||||
}.b_out: CompiledValue {
|
||||
layout: CompiledTypeLayout {
|
||||
ty: Enum {
|
||||
HdlNone,
|
||||
HdlSome(Bundle {0: UInt<1>, 1: Bool}),
|
||||
main_module: SimulationModuleState {
|
||||
base_targets: [
|
||||
Instance {
|
||||
name: <simulator>::enums,
|
||||
instantiated: Module {
|
||||
name: enums,
|
||||
..
|
||||
},
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(enums: enums).enums::b_out",
|
||||
ty: Enum {
|
||||
HdlNone,
|
||||
HdlSome(Bundle {0: UInt<1>, 1: Bool}),
|
||||
},
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
}.cd,
|
||||
Instance {
|
||||
name: <simulator>::enums,
|
||||
instantiated: Module {
|
||||
name: enums,
|
||||
..
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 7, len: 1 },
|
||||
},
|
||||
write: None,
|
||||
},
|
||||
Instance {
|
||||
name: <simulator>::enums,
|
||||
instantiated: Module {
|
||||
name: enums,
|
||||
..
|
||||
},
|
||||
}.cd: CompiledValue {
|
||||
layout: CompiledTypeLayout {
|
||||
ty: Bundle {
|
||||
/* offset = 0 */
|
||||
clk: Clock,
|
||||
/* offset = 1 */
|
||||
rst: SyncReset,
|
||||
},
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartLayout<BigSlots> {
|
||||
len: 2,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(enums: enums).enums::cd.clk",
|
||||
ty: Clock,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(enums: enums).enums::cd.rst",
|
||||
ty: SyncReset,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Bundle {
|
||||
fields: [
|
||||
CompiledBundleField {
|
||||
offset: TypeIndex {
|
||||
small_slots: StatePartIndex<SmallSlots>(0),
|
||||
big_slots: StatePartIndex<BigSlots>(0),
|
||||
},
|
||||
ty: CompiledTypeLayout {
|
||||
ty: Clock,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: Clock,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
},
|
||||
CompiledBundleField {
|
||||
offset: TypeIndex {
|
||||
small_slots: StatePartIndex<SmallSlots>(0),
|
||||
big_slots: StatePartIndex<BigSlots>(1),
|
||||
},
|
||||
ty: CompiledTypeLayout {
|
||||
ty: SyncReset,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: SyncReset,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
},
|
||||
],
|
||||
},
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 2 },
|
||||
},
|
||||
write: None,
|
||||
},
|
||||
Instance {
|
||||
name: <simulator>::enums,
|
||||
instantiated: Module {
|
||||
name: enums,
|
||||
..
|
||||
},
|
||||
}.cd.clk: CompiledValue {
|
||||
layout: CompiledTypeLayout {
|
||||
ty: Clock,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: Clock,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
|
||||
},
|
||||
write: None,
|
||||
},
|
||||
Instance {
|
||||
name: <simulator>::enums,
|
||||
instantiated: Module {
|
||||
name: enums,
|
||||
..
|
||||
},
|
||||
}.cd.rst: CompiledValue {
|
||||
layout: CompiledTypeLayout {
|
||||
ty: SyncReset,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartLayout<SmallSlots> {
|
||||
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|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
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|
||||
ty: SyncReset,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
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|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
|
||||
},
|
||||
write: None,
|
||||
},
|
||||
Instance {
|
||||
name: <simulator>::enums,
|
||||
instantiated: Module {
|
||||
name: enums,
|
||||
..
|
||||
},
|
||||
}.data_in: CompiledValue {
|
||||
layout: CompiledTypeLayout {
|
||||
ty: UInt<4>,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(enums: enums).enums::data_in",
|
||||
ty: UInt<4>,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
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|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 4, len: 1 },
|
||||
},
|
||||
write: None,
|
||||
},
|
||||
Instance {
|
||||
name: <simulator>::enums,
|
||||
instantiated: Module {
|
||||
name: enums,
|
||||
..
|
||||
},
|
||||
}.data_out: CompiledValue {
|
||||
layout: CompiledTypeLayout {
|
||||
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|
||||
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|
||||
small_slots: StatePartLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
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|
||||
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|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 6, len: 1 },
|
||||
},
|
||||
write: None,
|
||||
},
|
||||
Instance {
|
||||
name: <simulator>::enums,
|
||||
instantiated: Module {
|
||||
name: enums,
|
||||
..
|
||||
},
|
||||
}.en: CompiledValue {
|
||||
layout: CompiledTypeLayout {
|
||||
ty: Bool,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
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|
||||
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|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 2, len: 1 },
|
||||
},
|
||||
write: None,
|
||||
},
|
||||
Instance {
|
||||
name: <simulator>::enums,
|
||||
instantiated: Module {
|
||||
name: enums,
|
||||
..
|
||||
},
|
||||
}.which_in: CompiledValue {
|
||||
layout: CompiledTypeLayout {
|
||||
ty: UInt<2>,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
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|
||||
ty: UInt<2>,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
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|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 3, len: 1 },
|
||||
},
|
||||
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|
||||
},
|
||||
Instance {
|
||||
name: <simulator>::enums,
|
||||
instantiated: Module {
|
||||
name: enums,
|
||||
..
|
||||
},
|
||||
}.which_out: CompiledValue {
|
||||
layout: CompiledTypeLayout {
|
||||
ty: UInt<2>,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(enums: enums).enums::which_out",
|
||||
ty: UInt<2>,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 5, len: 1 },
|
||||
},
|
||||
write: None,
|
||||
}.en,
|
||||
Instance {
|
||||
name: <simulator>::enums,
|
||||
instantiated: Module {
|
||||
name: enums,
|
||||
..
|
||||
},
|
||||
}.which_in,
|
||||
Instance {
|
||||
name: <simulator>::enums,
|
||||
instantiated: Module {
|
||||
name: enums,
|
||||
..
|
||||
},
|
||||
}.data_in,
|
||||
Instance {
|
||||
name: <simulator>::enums,
|
||||
instantiated: Module {
|
||||
name: enums,
|
||||
..
|
||||
},
|
||||
}.which_out,
|
||||
Instance {
|
||||
name: <simulator>::enums,
|
||||
instantiated: Module {
|
||||
name: enums,
|
||||
..
|
||||
},
|
||||
}.data_out,
|
||||
Instance {
|
||||
name: <simulator>::enums,
|
||||
instantiated: Module {
|
||||
name: enums,
|
||||
..
|
||||
},
|
||||
}.b_out,
|
||||
],
|
||||
uninitialized_ios: {},
|
||||
io_targets: {
|
||||
Instance {
|
||||
name: <simulator>::enums,
|
||||
instantiated: Module {
|
||||
name: enums,
|
||||
..
|
||||
},
|
||||
}.b_out,
|
||||
Instance {
|
||||
name: <simulator>::enums,
|
||||
instantiated: Module {
|
||||
name: enums,
|
||||
..
|
||||
},
|
||||
}.cd,
|
||||
Instance {
|
||||
name: <simulator>::enums,
|
||||
instantiated: Module {
|
||||
name: enums,
|
||||
..
|
||||
},
|
||||
}.cd.clk,
|
||||
Instance {
|
||||
name: <simulator>::enums,
|
||||
instantiated: Module {
|
||||
name: enums,
|
||||
..
|
||||
},
|
||||
}.cd.rst,
|
||||
Instance {
|
||||
name: <simulator>::enums,
|
||||
instantiated: Module {
|
||||
name: enums,
|
||||
..
|
||||
},
|
||||
}.data_in,
|
||||
Instance {
|
||||
name: <simulator>::enums,
|
||||
instantiated: Module {
|
||||
name: enums,
|
||||
..
|
||||
},
|
||||
}.data_out,
|
||||
Instance {
|
||||
name: <simulator>::enums,
|
||||
instantiated: Module {
|
||||
name: enums,
|
||||
..
|
||||
},
|
||||
}.en,
|
||||
Instance {
|
||||
name: <simulator>::enums,
|
||||
instantiated: Module {
|
||||
name: enums,
|
||||
..
|
||||
},
|
||||
}.which_in,
|
||||
Instance {
|
||||
name: <simulator>::enums,
|
||||
instantiated: Module {
|
||||
name: enums,
|
||||
..
|
||||
},
|
||||
}.which_out,
|
||||
},
|
||||
did_initial_settle: true,
|
||||
},
|
||||
made_initial_step: true,
|
||||
needs_settle: false,
|
||||
extern_modules: [],
|
||||
state_ready_to_run: false,
|
||||
trace_decls: TraceModule {
|
||||
name: "enums",
|
||||
children: [
|
||||
|
|
|
|||
220
crates/fayalite/tests/sim/expected/extern_module.txt
Normal file
220
crates/fayalite/tests/sim/expected/extern_module.txt
Normal file
|
|
@ -0,0 +1,220 @@
|
|||
Simulation {
|
||||
state: State {
|
||||
insns: Insns {
|
||||
state_layout: StateLayout {
|
||||
ty: TypeLayout {
|
||||
small_slots: StatePartLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartLayout<BigSlots> {
|
||||
len: 2,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(extern_module: extern_module).extern_module::i",
|
||||
ty: Bool,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(extern_module: extern_module).extern_module::o",
|
||||
ty: Bool,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
memories: StatePartLayout<Memories> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
layout_data: [],
|
||||
..
|
||||
},
|
||||
},
|
||||
insns: [
|
||||
// at: module-XXXXXXXXXX.rs:1:1
|
||||
0: Return,
|
||||
],
|
||||
..
|
||||
},
|
||||
pc: 0,
|
||||
memory_write_log: [],
|
||||
memories: StatePart {
|
||||
value: [],
|
||||
},
|
||||
small_slots: StatePart {
|
||||
value: [],
|
||||
},
|
||||
big_slots: StatePart {
|
||||
value: [
|
||||
1,
|
||||
1,
|
||||
],
|
||||
},
|
||||
},
|
||||
io: Instance {
|
||||
name: <simulator>::extern_module,
|
||||
instantiated: Module {
|
||||
name: extern_module,
|
||||
..
|
||||
},
|
||||
},
|
||||
main_module: SimulationModuleState {
|
||||
base_targets: [
|
||||
Instance {
|
||||
name: <simulator>::extern_module,
|
||||
instantiated: Module {
|
||||
name: extern_module,
|
||||
..
|
||||
},
|
||||
}.i,
|
||||
Instance {
|
||||
name: <simulator>::extern_module,
|
||||
instantiated: Module {
|
||||
name: extern_module,
|
||||
..
|
||||
},
|
||||
}.o,
|
||||
],
|
||||
uninitialized_ios: {},
|
||||
io_targets: {
|
||||
Instance {
|
||||
name: <simulator>::extern_module,
|
||||
instantiated: Module {
|
||||
name: extern_module,
|
||||
..
|
||||
},
|
||||
}.i,
|
||||
Instance {
|
||||
name: <simulator>::extern_module,
|
||||
instantiated: Module {
|
||||
name: extern_module,
|
||||
..
|
||||
},
|
||||
}.o,
|
||||
},
|
||||
did_initial_settle: true,
|
||||
},
|
||||
extern_modules: [
|
||||
SimulationExternModuleState {
|
||||
module_state: SimulationModuleState {
|
||||
base_targets: [
|
||||
ModuleIO {
|
||||
name: extern_module::i,
|
||||
is_input: true,
|
||||
ty: Bool,
|
||||
..
|
||||
},
|
||||
ModuleIO {
|
||||
name: extern_module::o,
|
||||
is_input: false,
|
||||
ty: Bool,
|
||||
..
|
||||
},
|
||||
],
|
||||
uninitialized_ios: {},
|
||||
io_targets: {
|
||||
ModuleIO {
|
||||
name: extern_module::i,
|
||||
is_input: true,
|
||||
ty: Bool,
|
||||
..
|
||||
},
|
||||
ModuleIO {
|
||||
name: extern_module::o,
|
||||
is_input: false,
|
||||
ty: Bool,
|
||||
..
|
||||
},
|
||||
},
|
||||
did_initial_settle: true,
|
||||
},
|
||||
sim: ExternModuleSimulation {
|
||||
generator: SimGeneratorFn {
|
||||
args: (
|
||||
ModuleIO {
|
||||
name: extern_module::i,
|
||||
is_input: true,
|
||||
ty: Bool,
|
||||
..
|
||||
},
|
||||
ModuleIO {
|
||||
name: extern_module::o,
|
||||
is_input: false,
|
||||
ty: Bool,
|
||||
..
|
||||
},
|
||||
),
|
||||
f: ...,
|
||||
},
|
||||
source_location: SourceLocation(
|
||||
module-XXXXXXXXXX.rs:4:1,
|
||||
),
|
||||
},
|
||||
running_generator: Some(
|
||||
...,
|
||||
),
|
||||
wait_targets: {
|
||||
Instant(
|
||||
20.500000000000 μs,
|
||||
),
|
||||
},
|
||||
},
|
||||
],
|
||||
state_ready_to_run: false,
|
||||
trace_decls: TraceModule {
|
||||
name: "extern_module",
|
||||
children: [
|
||||
TraceModuleIO {
|
||||
name: "i",
|
||||
child: TraceBool {
|
||||
location: TraceScalarId(0),
|
||||
name: "i",
|
||||
flow: Source,
|
||||
},
|
||||
ty: Bool,
|
||||
flow: Source,
|
||||
},
|
||||
TraceModuleIO {
|
||||
name: "o",
|
||||
child: TraceBool {
|
||||
location: TraceScalarId(1),
|
||||
name: "o",
|
||||
flow: Sink,
|
||||
},
|
||||
ty: Bool,
|
||||
flow: Sink,
|
||||
},
|
||||
],
|
||||
},
|
||||
traces: [
|
||||
SimTrace {
|
||||
id: TraceScalarId(0),
|
||||
kind: BigBool {
|
||||
index: StatePartIndex<BigSlots>(0),
|
||||
},
|
||||
state: 0x1,
|
||||
last_state: 0x1,
|
||||
},
|
||||
SimTrace {
|
||||
id: TraceScalarId(1),
|
||||
kind: BigBool {
|
||||
index: StatePartIndex<BigSlots>(1),
|
||||
},
|
||||
state: 0x1,
|
||||
last_state: 0x1,
|
||||
},
|
||||
],
|
||||
trace_memories: {},
|
||||
trace_writers: [
|
||||
Running(
|
||||
VcdWriter {
|
||||
finished_init: true,
|
||||
timescale: 1 ps,
|
||||
..
|
||||
},
|
||||
),
|
||||
],
|
||||
instant: 20 μs,
|
||||
clocks_triggered: [],
|
||||
..
|
||||
}
|
||||
51
crates/fayalite/tests/sim/expected/extern_module.vcd
Normal file
51
crates/fayalite/tests/sim/expected/extern_module.vcd
Normal file
|
|
@ -0,0 +1,51 @@
|
|||
$timescale 1 ps $end
|
||||
$scope module extern_module $end
|
||||
$var wire 1 ! i $end
|
||||
$var wire 1 " o $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
$dumpvars
|
||||
0!
|
||||
1"
|
||||
$end
|
||||
#500000
|
||||
#1500000
|
||||
0"
|
||||
#2500000
|
||||
1"
|
||||
#3500000
|
||||
0"
|
||||
#4500000
|
||||
1"
|
||||
#5500000
|
||||
0"
|
||||
#6500000
|
||||
1"
|
||||
#7500000
|
||||
0"
|
||||
#8500000
|
||||
1"
|
||||
#9500000
|
||||
0"
|
||||
#10000000
|
||||
1!
|
||||
#10500000
|
||||
#11500000
|
||||
1"
|
||||
#12500000
|
||||
0"
|
||||
#13500000
|
||||
1"
|
||||
#14500000
|
||||
0"
|
||||
#15500000
|
||||
1"
|
||||
#16500000
|
||||
0"
|
||||
#17500000
|
||||
1"
|
||||
#18500000
|
||||
0"
|
||||
#19500000
|
||||
1"
|
||||
#20000000
|
||||
308
crates/fayalite/tests/sim/expected/extern_module2.txt
Normal file
308
crates/fayalite/tests/sim/expected/extern_module2.txt
Normal file
|
|
@ -0,0 +1,308 @@
|
|||
Simulation {
|
||||
state: State {
|
||||
insns: Insns {
|
||||
state_layout: StateLayout {
|
||||
ty: TypeLayout {
|
||||
small_slots: StatePartLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartLayout<BigSlots> {
|
||||
len: 3,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(extern_module2: extern_module2).extern_module2::en",
|
||||
ty: Bool,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(extern_module2: extern_module2).extern_module2::clk",
|
||||
ty: Clock,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(extern_module2: extern_module2).extern_module2::o",
|
||||
ty: UInt<8>,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
memories: StatePartLayout<Memories> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
layout_data: [],
|
||||
..
|
||||
},
|
||||
},
|
||||
insns: [
|
||||
// at: module-XXXXXXXXXX.rs:1:1
|
||||
0: Return,
|
||||
],
|
||||
..
|
||||
},
|
||||
pc: 0,
|
||||
memory_write_log: [],
|
||||
memories: StatePart {
|
||||
value: [],
|
||||
},
|
||||
small_slots: StatePart {
|
||||
value: [],
|
||||
},
|
||||
big_slots: StatePart {
|
||||
value: [
|
||||
0,
|
||||
1,
|
||||
101,
|
||||
],
|
||||
},
|
||||
},
|
||||
io: Instance {
|
||||
name: <simulator>::extern_module2,
|
||||
instantiated: Module {
|
||||
name: extern_module2,
|
||||
..
|
||||
},
|
||||
},
|
||||
main_module: SimulationModuleState {
|
||||
base_targets: [
|
||||
Instance {
|
||||
name: <simulator>::extern_module2,
|
||||
instantiated: Module {
|
||||
name: extern_module2,
|
||||
..
|
||||
},
|
||||
}.en,
|
||||
Instance {
|
||||
name: <simulator>::extern_module2,
|
||||
instantiated: Module {
|
||||
name: extern_module2,
|
||||
..
|
||||
},
|
||||
}.clk,
|
||||
Instance {
|
||||
name: <simulator>::extern_module2,
|
||||
instantiated: Module {
|
||||
name: extern_module2,
|
||||
..
|
||||
},
|
||||
}.o,
|
||||
],
|
||||
uninitialized_ios: {},
|
||||
io_targets: {
|
||||
Instance {
|
||||
name: <simulator>::extern_module2,
|
||||
instantiated: Module {
|
||||
name: extern_module2,
|
||||
..
|
||||
},
|
||||
}.clk,
|
||||
Instance {
|
||||
name: <simulator>::extern_module2,
|
||||
instantiated: Module {
|
||||
name: extern_module2,
|
||||
..
|
||||
},
|
||||
}.en,
|
||||
Instance {
|
||||
name: <simulator>::extern_module2,
|
||||
instantiated: Module {
|
||||
name: extern_module2,
|
||||
..
|
||||
},
|
||||
}.o,
|
||||
},
|
||||
did_initial_settle: true,
|
||||
},
|
||||
extern_modules: [
|
||||
SimulationExternModuleState {
|
||||
module_state: SimulationModuleState {
|
||||
base_targets: [
|
||||
ModuleIO {
|
||||
name: extern_module2::en,
|
||||
is_input: true,
|
||||
ty: Bool,
|
||||
..
|
||||
},
|
||||
ModuleIO {
|
||||
name: extern_module2::clk,
|
||||
is_input: true,
|
||||
ty: Clock,
|
||||
..
|
||||
},
|
||||
ModuleIO {
|
||||
name: extern_module2::o,
|
||||
is_input: false,
|
||||
ty: UInt<8>,
|
||||
..
|
||||
},
|
||||
],
|
||||
uninitialized_ios: {},
|
||||
io_targets: {
|
||||
ModuleIO {
|
||||
name: extern_module2::clk,
|
||||
is_input: true,
|
||||
ty: Clock,
|
||||
..
|
||||
},
|
||||
ModuleIO {
|
||||
name: extern_module2::en,
|
||||
is_input: true,
|
||||
ty: Bool,
|
||||
..
|
||||
},
|
||||
ModuleIO {
|
||||
name: extern_module2::o,
|
||||
is_input: false,
|
||||
ty: UInt<8>,
|
||||
..
|
||||
},
|
||||
},
|
||||
did_initial_settle: true,
|
||||
},
|
||||
sim: ExternModuleSimulation {
|
||||
generator: SimGeneratorFn {
|
||||
args: (
|
||||
ModuleIO {
|
||||
name: extern_module2::en,
|
||||
is_input: true,
|
||||
ty: Bool,
|
||||
..
|
||||
},
|
||||
ModuleIO {
|
||||
name: extern_module2::clk,
|
||||
is_input: true,
|
||||
ty: Clock,
|
||||
..
|
||||
},
|
||||
ModuleIO {
|
||||
name: extern_module2::o,
|
||||
is_input: false,
|
||||
ty: UInt<8>,
|
||||
..
|
||||
},
|
||||
),
|
||||
f: ...,
|
||||
},
|
||||
source_location: SourceLocation(
|
||||
module-XXXXXXXXXX.rs:5:1,
|
||||
),
|
||||
},
|
||||
running_generator: Some(
|
||||
...,
|
||||
),
|
||||
wait_targets: {
|
||||
Change {
|
||||
key: CompiledValue {
|
||||
layout: CompiledTypeLayout {
|
||||
ty: Clock,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(extern_module2: extern_module2).extern_module2::clk",
|
||||
ty: Clock,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
|
||||
},
|
||||
write: None,
|
||||
},
|
||||
value: SimValue {
|
||||
ty: Clock,
|
||||
bits: 0x1,
|
||||
},
|
||||
},
|
||||
},
|
||||
},
|
||||
],
|
||||
state_ready_to_run: false,
|
||||
trace_decls: TraceModule {
|
||||
name: "extern_module2",
|
||||
children: [
|
||||
TraceModuleIO {
|
||||
name: "en",
|
||||
child: TraceBool {
|
||||
location: TraceScalarId(0),
|
||||
name: "en",
|
||||
flow: Source,
|
||||
},
|
||||
ty: Bool,
|
||||
flow: Source,
|
||||
},
|
||||
TraceModuleIO {
|
||||
name: "clk",
|
||||
child: TraceClock {
|
||||
location: TraceScalarId(1),
|
||||
name: "clk",
|
||||
flow: Source,
|
||||
},
|
||||
ty: Clock,
|
||||
flow: Source,
|
||||
},
|
||||
TraceModuleIO {
|
||||
name: "o",
|
||||
child: TraceUInt {
|
||||
location: TraceScalarId(2),
|
||||
name: "o",
|
||||
ty: UInt<8>,
|
||||
flow: Sink,
|
||||
},
|
||||
ty: UInt<8>,
|
||||
flow: Sink,
|
||||
},
|
||||
],
|
||||
},
|
||||
traces: [
|
||||
SimTrace {
|
||||
id: TraceScalarId(0),
|
||||
kind: BigBool {
|
||||
index: StatePartIndex<BigSlots>(0),
|
||||
},
|
||||
state: 0x0,
|
||||
last_state: 0x0,
|
||||
},
|
||||
SimTrace {
|
||||
id: TraceScalarId(1),
|
||||
kind: BigClock {
|
||||
index: StatePartIndex<BigSlots>(1),
|
||||
},
|
||||
state: 0x1,
|
||||
last_state: 0x1,
|
||||
},
|
||||
SimTrace {
|
||||
id: TraceScalarId(2),
|
||||
kind: BigUInt {
|
||||
index: StatePartIndex<BigSlots>(2),
|
||||
ty: UInt<8>,
|
||||
},
|
||||
state: 0x65,
|
||||
last_state: 0x65,
|
||||
},
|
||||
],
|
||||
trace_memories: {},
|
||||
trace_writers: [
|
||||
Running(
|
||||
VcdWriter {
|
||||
finished_init: true,
|
||||
timescale: 1 ps,
|
||||
..
|
||||
},
|
||||
),
|
||||
],
|
||||
instant: 60 μs,
|
||||
clocks_triggered: [],
|
||||
..
|
||||
}
|
||||
150
crates/fayalite/tests/sim/expected/extern_module2.vcd
Normal file
150
crates/fayalite/tests/sim/expected/extern_module2.vcd
Normal file
|
|
@ -0,0 +1,150 @@
|
|||
$timescale 1 ps $end
|
||||
$scope module extern_module2 $end
|
||||
$var wire 1 ! en $end
|
||||
$var wire 1 " clk $end
|
||||
$var wire 8 # o $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
$dumpvars
|
||||
1!
|
||||
0"
|
||||
b1001000 #
|
||||
$end
|
||||
#1000000
|
||||
1"
|
||||
b1100101 #
|
||||
#2000000
|
||||
0"
|
||||
#3000000
|
||||
1"
|
||||
b1101100 #
|
||||
#4000000
|
||||
0"
|
||||
#5000000
|
||||
1"
|
||||
#6000000
|
||||
0"
|
||||
#7000000
|
||||
1"
|
||||
b1101111 #
|
||||
#8000000
|
||||
0"
|
||||
#9000000
|
||||
1"
|
||||
b101100 #
|
||||
#10000000
|
||||
0!
|
||||
0"
|
||||
#11000000
|
||||
1"
|
||||
#12000000
|
||||
0"
|
||||
#13000000
|
||||
1"
|
||||
#14000000
|
||||
0"
|
||||
#15000000
|
||||
1"
|
||||
#16000000
|
||||
0"
|
||||
#17000000
|
||||
1"
|
||||
#18000000
|
||||
0"
|
||||
#19000000
|
||||
1"
|
||||
#20000000
|
||||
1!
|
||||
0"
|
||||
#21000000
|
||||
1"
|
||||
b100000 #
|
||||
#22000000
|
||||
0"
|
||||
#23000000
|
||||
1"
|
||||
b1010111 #
|
||||
#24000000
|
||||
0"
|
||||
#25000000
|
||||
1"
|
||||
b1101111 #
|
||||
#26000000
|
||||
0"
|
||||
#27000000
|
||||
1"
|
||||
b1110010 #
|
||||
#28000000
|
||||
0"
|
||||
#29000000
|
||||
1"
|
||||
b1101100 #
|
||||
#30000000
|
||||
0!
|
||||
0"
|
||||
#31000000
|
||||
1"
|
||||
#32000000
|
||||
0"
|
||||
#33000000
|
||||
1"
|
||||
#34000000
|
||||
0"
|
||||
#35000000
|
||||
1"
|
||||
#36000000
|
||||
0"
|
||||
#37000000
|
||||
1"
|
||||
#38000000
|
||||
0"
|
||||
#39000000
|
||||
1"
|
||||
#40000000
|
||||
1!
|
||||
0"
|
||||
#41000000
|
||||
1"
|
||||
b1100100 #
|
||||
#42000000
|
||||
0"
|
||||
#43000000
|
||||
1"
|
||||
b100001 #
|
||||
#44000000
|
||||
0"
|
||||
#45000000
|
||||
1"
|
||||
b1010 #
|
||||
#46000000
|
||||
0"
|
||||
#47000000
|
||||
1"
|
||||
b1001000 #
|
||||
#48000000
|
||||
0"
|
||||
#49000000
|
||||
1"
|
||||
b1100101 #
|
||||
#50000000
|
||||
0!
|
||||
0"
|
||||
#51000000
|
||||
1"
|
||||
#52000000
|
||||
0"
|
||||
#53000000
|
||||
1"
|
||||
#54000000
|
||||
0"
|
||||
#55000000
|
||||
1"
|
||||
#56000000
|
||||
0"
|
||||
#57000000
|
||||
1"
|
||||
#58000000
|
||||
0"
|
||||
#59000000
|
||||
1"
|
||||
#60000000
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -598,514 +598,79 @@ Simulation {
|
|||
..
|
||||
},
|
||||
},
|
||||
uninitialized_inputs: {},
|
||||
io_targets: {
|
||||
Instance {
|
||||
name: <simulator>::memories2,
|
||||
instantiated: Module {
|
||||
name: memories2,
|
||||
..
|
||||
},
|
||||
}.rw: CompiledValue {
|
||||
layout: CompiledTypeLayout {
|
||||
ty: Bundle {
|
||||
/* offset = 0 */
|
||||
addr: UInt<3>,
|
||||
/* offset = 3 */
|
||||
en: Bool,
|
||||
/* offset = 4 */
|
||||
clk: Clock,
|
||||
#[hdl(flip)] /* offset = 5 */
|
||||
rdata: UInt<2>,
|
||||
/* offset = 7 */
|
||||
wmode: Bool,
|
||||
/* offset = 8 */
|
||||
wdata: UInt<2>,
|
||||
/* offset = 10 */
|
||||
wmask: Bool,
|
||||
main_module: SimulationModuleState {
|
||||
base_targets: [
|
||||
Instance {
|
||||
name: <simulator>::memories2,
|
||||
instantiated: Module {
|
||||
name: memories2,
|
||||
..
|
||||
},
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartLayout<BigSlots> {
|
||||
len: 7,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(memories2: memories2).memories2::rw.addr",
|
||||
ty: UInt<3>,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(memories2: memories2).memories2::rw.en",
|
||||
ty: Bool,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(memories2: memories2).memories2::rw.clk",
|
||||
ty: Clock,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(memories2: memories2).memories2::rw.rdata",
|
||||
ty: UInt<2>,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(memories2: memories2).memories2::rw.wmode",
|
||||
ty: Bool,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(memories2: memories2).memories2::rw.wdata",
|
||||
ty: UInt<2>,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(memories2: memories2).memories2::rw.wmask",
|
||||
ty: Bool,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
}.rw,
|
||||
],
|
||||
uninitialized_ios: {},
|
||||
io_targets: {
|
||||
Instance {
|
||||
name: <simulator>::memories2,
|
||||
instantiated: Module {
|
||||
name: memories2,
|
||||
..
|
||||
},
|
||||
body: Bundle {
|
||||
fields: [
|
||||
CompiledBundleField {
|
||||
offset: TypeIndex {
|
||||
small_slots: StatePartIndex<SmallSlots>(0),
|
||||
big_slots: StatePartIndex<BigSlots>(0),
|
||||
},
|
||||
ty: CompiledTypeLayout {
|
||||
ty: UInt<3>,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: UInt<3>,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
},
|
||||
CompiledBundleField {
|
||||
offset: TypeIndex {
|
||||
small_slots: StatePartIndex<SmallSlots>(0),
|
||||
big_slots: StatePartIndex<BigSlots>(1),
|
||||
},
|
||||
ty: CompiledTypeLayout {
|
||||
ty: Bool,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: Bool,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
},
|
||||
CompiledBundleField {
|
||||
offset: TypeIndex {
|
||||
small_slots: StatePartIndex<SmallSlots>(0),
|
||||
big_slots: StatePartIndex<BigSlots>(2),
|
||||
},
|
||||
ty: CompiledTypeLayout {
|
||||
ty: Clock,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: Clock,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
},
|
||||
CompiledBundleField {
|
||||
offset: TypeIndex {
|
||||
small_slots: StatePartIndex<SmallSlots>(0),
|
||||
big_slots: StatePartIndex<BigSlots>(3),
|
||||
},
|
||||
ty: CompiledTypeLayout {
|
||||
ty: UInt<2>,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: UInt<2>,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
},
|
||||
CompiledBundleField {
|
||||
offset: TypeIndex {
|
||||
small_slots: StatePartIndex<SmallSlots>(0),
|
||||
big_slots: StatePartIndex<BigSlots>(4),
|
||||
},
|
||||
ty: CompiledTypeLayout {
|
||||
ty: Bool,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: Bool,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
},
|
||||
CompiledBundleField {
|
||||
offset: TypeIndex {
|
||||
small_slots: StatePartIndex<SmallSlots>(0),
|
||||
big_slots: StatePartIndex<BigSlots>(5),
|
||||
},
|
||||
ty: CompiledTypeLayout {
|
||||
ty: UInt<2>,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: UInt<2>,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
},
|
||||
CompiledBundleField {
|
||||
offset: TypeIndex {
|
||||
small_slots: StatePartIndex<SmallSlots>(0),
|
||||
big_slots: StatePartIndex<BigSlots>(6),
|
||||
},
|
||||
ty: CompiledTypeLayout {
|
||||
ty: Bool,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: Bool,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
},
|
||||
],
|
||||
}.rw,
|
||||
Instance {
|
||||
name: <simulator>::memories2,
|
||||
instantiated: Module {
|
||||
name: memories2,
|
||||
..
|
||||
},
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 7 },
|
||||
},
|
||||
write: None,
|
||||
},
|
||||
Instance {
|
||||
name: <simulator>::memories2,
|
||||
instantiated: Module {
|
||||
name: memories2,
|
||||
..
|
||||
},
|
||||
}.rw.addr: CompiledValue {
|
||||
layout: CompiledTypeLayout {
|
||||
ty: UInt<3>,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: UInt<3>,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
|
||||
},
|
||||
write: None,
|
||||
},
|
||||
Instance {
|
||||
name: <simulator>::memories2,
|
||||
instantiated: Module {
|
||||
name: memories2,
|
||||
..
|
||||
},
|
||||
}.rw.clk: CompiledValue {
|
||||
layout: CompiledTypeLayout {
|
||||
ty: Clock,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: Clock,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 2, len: 1 },
|
||||
},
|
||||
write: None,
|
||||
},
|
||||
Instance {
|
||||
name: <simulator>::memories2,
|
||||
instantiated: Module {
|
||||
name: memories2,
|
||||
..
|
||||
},
|
||||
}.rw.en: CompiledValue {
|
||||
layout: CompiledTypeLayout {
|
||||
ty: Bool,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: Bool,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
|
||||
},
|
||||
write: None,
|
||||
},
|
||||
Instance {
|
||||
name: <simulator>::memories2,
|
||||
instantiated: Module {
|
||||
name: memories2,
|
||||
..
|
||||
},
|
||||
}.rw.rdata: CompiledValue {
|
||||
layout: CompiledTypeLayout {
|
||||
ty: UInt<2>,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: UInt<2>,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 3, len: 1 },
|
||||
},
|
||||
write: None,
|
||||
},
|
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||||
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||||
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|
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|||
File diff suppressed because it is too large
Load diff
|
|
@ -216,313 +216,58 @@ Simulation {
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|
||||
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|
||||
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
..
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
|
|
|
|||
1492
crates/fayalite/tests/sim/expected/ripple_counter.txt
Normal file
1492
crates/fayalite/tests/sim/expected/ripple_counter.txt
Normal file
File diff suppressed because it is too large
Load diff
1753
crates/fayalite/tests/sim/expected/ripple_counter.vcd
Normal file
1753
crates/fayalite/tests/sim/expected/ripple_counter.vcd
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -265,247 +265,72 @@ Simulation {
|
|||
..
|
||||
},
|
||||
},
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
..
|
||||
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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],
|
||||
..
|
||||
},
|
||||
}.cd,
|
||||
Instance {
|
||||
name: <simulator>::shift_register,
|
||||
instantiated: Module {
|
||||
name: shift_register,
|
||||
..
|
||||
},
|
||||
body: Bundle {
|
||||
fields: [
|
||||
CompiledBundleField {
|
||||
offset: TypeIndex {
|
||||
small_slots: StatePartIndex<SmallSlots>(0),
|
||||
big_slots: StatePartIndex<BigSlots>(0),
|
||||
},
|
||||
ty: CompiledTypeLayout {
|
||||
ty: Clock,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: Clock,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
},
|
||||
CompiledBundleField {
|
||||
offset: TypeIndex {
|
||||
small_slots: StatePartIndex<SmallSlots>(0),
|
||||
big_slots: StatePartIndex<BigSlots>(1),
|
||||
},
|
||||
ty: CompiledTypeLayout {
|
||||
ty: SyncReset,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: SyncReset,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
},
|
||||
],
|
||||
}.d,
|
||||
Instance {
|
||||
name: <simulator>::shift_register,
|
||||
instantiated: Module {
|
||||
name: shift_register,
|
||||
..
|
||||
},
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 2 },
|
||||
},
|
||||
write: None,
|
||||
},
|
||||
Instance {
|
||||
name: <simulator>::shift_register,
|
||||
instantiated: Module {
|
||||
name: shift_register,
|
||||
..
|
||||
},
|
||||
}.cd.clk: CompiledValue {
|
||||
layout: CompiledTypeLayout {
|
||||
ty: Clock,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: Clock,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
|
||||
},
|
||||
write: None,
|
||||
},
|
||||
Instance {
|
||||
name: <simulator>::shift_register,
|
||||
instantiated: Module {
|
||||
name: shift_register,
|
||||
..
|
||||
},
|
||||
}.cd.rst: CompiledValue {
|
||||
layout: CompiledTypeLayout {
|
||||
ty: SyncReset,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: SyncReset,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
|
||||
},
|
||||
write: None,
|
||||
},
|
||||
Instance {
|
||||
name: <simulator>::shift_register,
|
||||
instantiated: Module {
|
||||
name: shift_register,
|
||||
..
|
||||
},
|
||||
}.d: CompiledValue {
|
||||
layout: CompiledTypeLayout {
|
||||
ty: Bool,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(shift_register: shift_register).shift_register::d",
|
||||
ty: Bool,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 2, len: 1 },
|
||||
},
|
||||
write: None,
|
||||
},
|
||||
Instance {
|
||||
name: <simulator>::shift_register,
|
||||
instantiated: Module {
|
||||
name: shift_register,
|
||||
..
|
||||
},
|
||||
}.q: CompiledValue {
|
||||
layout: CompiledTypeLayout {
|
||||
ty: Bool,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(shift_register: shift_register).shift_register::q",
|
||||
ty: Bool,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 3, len: 1 },
|
||||
},
|
||||
write: None,
|
||||
}.q,
|
||||
],
|
||||
uninitialized_ios: {},
|
||||
io_targets: {
|
||||
Instance {
|
||||
name: <simulator>::shift_register,
|
||||
instantiated: Module {
|
||||
name: shift_register,
|
||||
..
|
||||
},
|
||||
}.cd,
|
||||
Instance {
|
||||
name: <simulator>::shift_register,
|
||||
instantiated: Module {
|
||||
name: shift_register,
|
||||
..
|
||||
},
|
||||
}.cd.clk,
|
||||
Instance {
|
||||
name: <simulator>::shift_register,
|
||||
instantiated: Module {
|
||||
name: shift_register,
|
||||
..
|
||||
},
|
||||
}.cd.rst,
|
||||
Instance {
|
||||
name: <simulator>::shift_register,
|
||||
instantiated: Module {
|
||||
name: shift_register,
|
||||
..
|
||||
},
|
||||
}.d,
|
||||
Instance {
|
||||
name: <simulator>::shift_register,
|
||||
instantiated: Module {
|
||||
name: shift_register,
|
||||
..
|
||||
},
|
||||
}.q,
|
||||
},
|
||||
did_initial_settle: true,
|
||||
},
|
||||
made_initial_step: true,
|
||||
needs_settle: false,
|
||||
extern_modules: [],
|
||||
state_ready_to_run: false,
|
||||
trace_decls: TraceModule {
|
||||
name: "shift_register",
|
||||
children: [
|
||||
|
|
|
|||
|
|
@ -160,7 +160,8 @@
|
|||
"data": {
|
||||
"$kind": "Struct",
|
||||
"verilog_name": "Visible",
|
||||
"parameters": "Visible"
|
||||
"parameters": "Visible",
|
||||
"simulation": "Visible"
|
||||
}
|
||||
},
|
||||
"ExternModuleParameter": {
|
||||
|
|
@ -1269,6 +1270,11 @@
|
|||
"$kind": "Opaque"
|
||||
},
|
||||
"generics": "<T: ?Sized + crate::phantom_const::PhantomConstValue>"
|
||||
},
|
||||
"ExternModuleSimulation": {
|
||||
"data": {
|
||||
"$kind": "Opaque"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
Loading…
Reference in a new issue