programmerjake

programmerjake pushed to add-mem-and-io at programmerjake/cpu

2026-02-26 02:06:47 +00:00

b07ef2b363 add main_memory_and_io::simple_uart::receiver* and test for receiver_no_queue

programmerjake pushed to add-mem-and-io at programmerjake/cpu

2026-02-25 23:23:00 +00:00

e6caa320ef add main_memory_and_io::simple_uart::{transmitter, uart_clock_gen} and tests

programmerjake pushed to add-mem-and-io at programmerjake/cpu

2026-02-25 23:21:13 +00:00

d61475faf4 add main_memory_and_io::simple_uart::{transmitter, uart_clock_gen} and tests

programmerjake created branch add-mem-and-io in programmerjake/cpu

2026-02-25 08:09:49 +00:00

programmerjake pushed to add-mem-and-io at programmerjake/cpu

2026-02-25 08:09:49 +00:00

1d8a948443 add WIP simple_uart

3fcd1c7338 add MemoryOperationStart.rw_mask

cd7823e81d move MemoryInterface and related types to crate::main_memory_and_io

2a1813bff3 update to latest fayalite

e69c92c8da add fetch::fetch and fetch::l1_i_cache with some testing

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programmerjake commented on issue libre-chip/grant-tracking#15

2026-02-25 08:07:49 +00:00

NLnet 2024-12-324 memory system: main memory and IO devices

Since you haven't responded yet, I'm assuming it's ok and going ahead and working on it.

programmerjake deleted branch make-vcd-diff-friendly from programmerjake/fayalite

2026-02-24 04:18:28 +00:00

programmerjake pushed to master at libre-chip/fayalite

2026-02-24 04:18:27 +00:00

dbed947408 change VCD id generation to be based on hashing the path, making them better for git diff

cb4e1f42c0 silence unused import warning

8c270b0e35 silence warning for enums with only one variant

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programmerjake automatically merged pull request libre-chip/fayalite#65

2026-02-24 04:18:26 +00:00

programmerjake created pull request libre-chip/fayalite#65

2026-02-24 04:10:30 +00:00

change VCD id generation to be based on hashing the path, making them better for git diff

programmerjake created branch make-vcd-diff-friendly in programmerjake/fayalite

2026-02-24 04:08:24 +00:00

programmerjake pushed to make-vcd-diff-friendly at programmerjake/fayalite

2026-02-24 04:08:24 +00:00

dbed947408 change VCD id generation to be based on hashing the path, making them better for git diff

cb4e1f42c0 silence unused import warning

8c270b0e35 silence warning for enums with only one variant

c632e5d570 speed up simulation by optimizing SimulationImpl::read_traces

1bc835803b speed up LazyInterned by redoing caching using RwLock and add a thread-local cache

Compare 10 commits »

programmerjake commented on issue libre-chip/grant-tracking#15

2026-02-23 19:39:17 +00:00

NLnet 2024-12-324 memory system: main memory and IO devices

@HaeckseAlex as I mentioned on Zulip:

@**Tobias Alexandra…

programmerjake commented on issue libre-chip/grant-tracking#11

2026-02-22 21:32:50 +00:00

NLnet 2024-12-324 Create the fetch and i-cache logic.

In libre-chip/cpu#9 I implemented a direct-mapped L1 I-Cache designed to be integrated into the fetch pipeline control logic from https://git.libre-chip.org/libre-c…

programmerjake closed issue libre-chip/grant-tracking#11

2026-02-22 21:32:50 +00:00

NLnet 2024-12-324 Create the fetch and i-cache logic.

programmerjake merged pull request libre-chip/cpu#9

2026-02-22 02:58:21 +00:00

add fetch::fetch and fetch::l1_i_cache with some testing

programmerjake pushed to master at libre-chip/cpu

2026-02-22 02:58:21 +00:00

e69c92c8da add fetch::fetch and fetch::l1_i_cache with some testing

c62d33048c update fayalite to c632e5d570 to speed up simulation

Compare 2 commits »

programmerjake deleted branch create-fetch-and-i-cache-logic from programmerjake/cpu

2026-02-22 02:58:21 +00:00

programmerjake pushed to create-fetch-and-i-cache-logic at programmerjake/cpu

2026-02-22 02:32:37 +00:00

e69c92c8da add fetch::fetch and fetch::l1_i_cache with some testing

programmerjake pushed to create-fetch-and-i-cache-logic at programmerjake/cpu

2026-02-22 02:13:36 +00:00

198fa64899 add fetch::fetch and fetch::l1_i_cache with some testing