forked from libre-chip/cpu
add main_memory_and_io::simple_uart::receiver* and test for receiver_no_queue
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e6caa320ef
commit
b07ef2b363
SSH key fingerprint:
SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
3 changed files with 189001 additions and 2 deletions
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@ -1,8 +1,14 @@
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// SPDX-License-Identifier: LGPL-3.0-or-later
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// See Notices.txt for copyright information
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use std::num::NonZeroUsize;
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use crate::config::CpuConfig;
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use fayalite::{int::UIntInRange, prelude::*, util::ready_valid::ReadyValid};
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use fayalite::{
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int::UIntInRange,
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prelude::*,
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util::ready_valid::{ReadyValid, queue},
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};
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const TICKS_PER_BAUD: usize = 16;
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const PRECISION_BITS: usize = 16;
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@ -140,6 +146,177 @@ pub fn transmitter() {
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}
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}
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/// `rx_synchronized` is [`peripherals::Uart::rx`], but after being synchronized to `cd.clk`.
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/// `output_byte` is `HdlSome` for 1 clock cycle for every received byte.
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#[hdl_module]
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pub fn receiver_no_queue() {
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#[hdl]
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let cd: ClockDomain = m.input();
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#[hdl]
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let tick: Bool = m.input();
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#[hdl]
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let rx_synchronized: Bool = m.input();
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#[hdl]
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let output_byte: HdlOption<UInt<8>> = m.output();
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const BITS_PER_BYTE: usize = 8;
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#[hdl]
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let output_byte_reg: HdlOption<UInt<{ BITS_PER_BYTE }>> =
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reg_builder().clock_domain(cd).reset(HdlNone());
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connect(output_byte, output_byte_reg);
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connect(output_byte_reg, HdlNone()); // by default always reset to HdlNone()
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#[hdl]
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let tick_count_reg = reg_builder()
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.clock_domain(cd)
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.reset(0u8.cast_to(UInt::range(0..TICKS_PER_BAUD)));
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#[hdl]
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let shift_reg: UInt<{ BITS_PER_BYTE }> = reg_builder().clock_domain(cd).reset(0u8);
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#[hdl]
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enum State {
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WaitingForStartBit,
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StartBit,
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DataBits(UIntInRange<0, { BITS_PER_BYTE }>),
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StopBit,
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}
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#[hdl]
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let state_reg = reg_builder()
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.clock_domain(cd)
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.reset(State.WaitingForStartBit());
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#[hdl]
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if tick {
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#[hdl]
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match state_reg {
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State::WaitingForStartBit => {
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connect(tick_count_reg, tick_count_reg.ty().zero());
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#[hdl]
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if !rx_synchronized {
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connect(state_reg, State.StartBit());
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}
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}
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State::StartBit =>
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{
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#[hdl]
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if tick_count_reg.cmp_eq(TICKS_PER_BAUD - 1) {
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connect(tick_count_reg, tick_count_reg.ty().zero());
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connect(state_reg, State.DataBits(0u8.cast_to(State.DataBits)));
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} else {
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connect_any(tick_count_reg, tick_count_reg + 1u8);
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}
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}
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State::DataBits(count) => {
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#[hdl]
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if tick_count_reg.cmp_eq(TICKS_PER_BAUD - 1) {
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connect(tick_count_reg, tick_count_reg.ty().zero());
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#[hdl]
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if count.cmp_eq(BITS_PER_BYTE - 1) {
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connect(state_reg, State.StopBit());
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connect(output_byte_reg, HdlSome(shift_reg));
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} else {
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connect(
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state_reg,
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State.DataBits((count.cast_to(UInt[8]) + 1u8).cast_to(State.DataBits)),
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);
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}
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} else {
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connect_any(tick_count_reg, tick_count_reg + 1u8);
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}
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#[hdl]
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if tick_count_reg.cmp_eq(TICKS_PER_BAUD / 2) {
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connect_any(
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shift_reg,
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(shift_reg >> 1) | (rx_synchronized.cast_to_static::<UInt<1>>() << 7),
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);
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}
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}
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State::StopBit => {
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#[hdl]
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if tick_count_reg.cmp_eq(TICKS_PER_BAUD / 2) {
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// go to WaitingForStartBit in the middle of the stop bit so we can adjust if the sender is faster than us.
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connect(tick_count_reg, tick_count_reg.ty().zero());
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connect(state_reg, State.WaitingForStartBit());
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} else {
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connect_any(tick_count_reg, tick_count_reg + 1u8);
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}
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}
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}
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}
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}
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#[hdl]
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pub enum ReceiverQueueStatus {
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QueueEmpty,
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QueueNotEmpty,
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QueueAlmostFull,
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QueueFull,
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QueueOverflowed,
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}
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/// `rx_synchronized` is [`peripherals::Uart::rx`], but after being synchronized to `cd.clk`.
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#[hdl_module]
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pub fn receiver(queue_capacity: NonZeroUsize) {
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#[hdl]
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let cd: ClockDomain = m.input();
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#[hdl]
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let tick: Bool = m.input();
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#[hdl]
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let rx_synchronized: Bool = m.input();
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#[hdl]
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let output_byte: ReadyValid<UInt<8>> = m.output();
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#[hdl]
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let queue_status: ReceiverQueueStatus = m.output();
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#[hdl]
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let queue = instance(queue(UInt::<8>::new_static(), queue_capacity, false, false));
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connect(queue.cd, cd);
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connect(output_byte, queue.out);
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#[hdl]
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let queue_overflowed_reg = reg_builder().clock_domain(cd).reset(false);
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#[hdl]
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if queue_overflowed_reg {
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connect(queue_status, ReceiverQueueStatus.QueueOverflowed());
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} else if queue.count.cmp_eq(0u8) {
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connect(queue_status, ReceiverQueueStatus.QueueEmpty());
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} else if queue.count.cmp_eq(queue_capacity) {
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connect(queue_status, ReceiverQueueStatus.QueueFull());
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} else if queue.count.cmp_eq(queue_capacity.get() - 1) {
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connect(queue_status, ReceiverQueueStatus.QueueAlmostFull());
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} else {
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connect(queue_status, ReceiverQueueStatus.QueueNotEmpty());
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}
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#[hdl]
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if ReadyValid::firing(output_byte) {
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// clear overflow when a byte is read from the queue
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connect(queue_overflowed_reg, false);
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}
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// we ignore queue.inp.ready other than noting an overflow when there was data but the queue wasn't ready
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#[hdl]
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if !queue.inp.ready {
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#[hdl]
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if let HdlSome(_) = queue.inp.data {
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connect(queue_overflowed_reg, true);
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}
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}
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#[hdl]
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let inner = instance(receiver_no_queue());
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connect(inner.cd, cd);
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connect(inner.tick, tick);
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connect(inner.rx_synchronized, rx_synchronized);
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connect(queue.inp.data, inner.output_byte);
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}
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#[hdl_module]
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pub fn simple_uart(
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config: PhantomConst<CpuConfig>,
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188659
crates/cpu/tests/expected/receiver_no_queue_and_uart_clock_gen.vcd
generated
Normal file
188659
crates/cpu/tests/expected/receiver_no_queue_and_uart_clock_gen.vcd
generated
Normal file
File diff suppressed because it is too large
Load diff
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@ -1,8 +1,9 @@
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// SPDX-License-Identifier: LGPL-3.0-or-later
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// See Notices.txt for copyright information
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use cpu::main_memory_and_io::simple_uart::{transmitter, uart_clock_gen};
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use cpu::main_memory_and_io::simple_uart::{receiver_no_queue, transmitter, uart_clock_gen};
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use fayalite::{
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intern::{Intern, Interned},
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prelude::*,
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sim::vcd::VcdWriterDecls,
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util::{RcWriter, ready_valid::ReadyValid},
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@ -18,6 +19,23 @@ const BAUD_RATE: f64 = 9600.0;
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const BAUD_HALF_PERIOD: SimDuration = half_period(BAUD_RATE);
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const BAUD_PERIOD: SimDuration = BAUD_HALF_PERIOD.saturating_add(BAUD_HALF_PERIOD);
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const fn baud_period_slow_percentage(percent: i128) -> SimDuration {
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let v = BAUD_PERIOD.as_attos();
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let v = v.strict_add_signed(v as i128 * percent / 100);
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SimDuration::from_attos(v)
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}
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/// 3% slow BAUD_PERIOD
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const BAUD_PERIOD_SLOW: SimDuration = baud_period_slow_percentage(3);
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/// 3% fast BAUD_PERIOD
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const BAUD_PERIOD_FAST: SimDuration = baud_period_slow_percentage(-3);
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const _: () = {
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assert!(BAUD_HALF_PERIOD.as_attos() < BAUD_PERIOD_FAST.as_attos());
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assert!(BAUD_PERIOD_FAST.as_attos() < BAUD_PERIOD.as_attos());
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assert!(BAUD_PERIOD.as_attos() < BAUD_PERIOD_SLOW.as_attos());
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};
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fn clock_input_properties() -> PhantomConst<peripherals::ClockInputProperties> {
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peripherals::ClockInput::new(CLOCK_FREQUENCY).properties
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}
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@ -171,5 +189,150 @@ fn test_transmitter_and_uart_clock_gen() {
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}
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}
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#[hdl_module(extern)]
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fn receiver_test_cases(text: Interned<str>) {
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#[hdl]
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let rx: Bool = m.output();
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#[hdl]
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let cur_byte: UInt<8> = m.output();
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m.extern_module_simulation_fn(
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(rx, cur_byte, text),
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async |(rx, cur_byte, text), mut sim| {
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// ensure the receiver can properly handle slightly fast or slow baud rates
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let baud_periods = [
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BAUD_PERIOD_FAST,
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BAUD_PERIOD_FAST,
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BAUD_PERIOD_FAST,
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BAUD_PERIOD_FAST,
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BAUD_PERIOD,
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BAUD_PERIOD,
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BAUD_PERIOD,
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BAUD_PERIOD,
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BAUD_PERIOD_SLOW,
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BAUD_PERIOD_SLOW,
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BAUD_PERIOD_SLOW,
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BAUD_PERIOD_SLOW,
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]
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.iter()
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.copied()
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.cycle();
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sim.write(rx, true).await;
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sim.write(cur_byte, 0u8).await;
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// allow time for reset and stuff
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sim.advance_time(SimDuration::from_micros(100)).await;
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for (byte, baud_period) in text.bytes().cycle().zip(baud_periods) {
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sim.write(cur_byte, byte).await;
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sim.write(rx, false).await; // start bit
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sim.advance_time(baud_period).await;
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for i in 0..u8::BITS {
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sim.write(rx, byte & (1 << i) != 0).await; // data bit
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sim.advance_time(baud_period).await;
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}
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sim.write(rx, true).await; // stop bit
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sim.advance_time(baud_period).await;
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}
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},
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);
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}
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#[hdl_module]
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fn receiver_no_queue_and_uart_clock_gen(text: Interned<str>) {
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#[hdl]
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let cd: ClockDomain = m.input();
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#[hdl]
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let rx: Bool = m.output();
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#[hdl]
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let output_byte: HdlOption<UInt<8>> = m.output();
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#[hdl]
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let cur_byte: UInt<8> = m.output();
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#[hdl]
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let reference_baud_rate_clk: Clock = m.output();
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#[hdl]
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let test_cases = instance(receiver_test_cases(text));
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connect(rx, test_cases.rx);
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connect(cur_byte, test_cases.cur_byte);
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#[hdl]
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let reference_baud_rate_clk_gen = instance(reference_baud_rate_clk_gen());
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connect(
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reference_baud_rate_clk,
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reference_baud_rate_clk_gen.reference_baud_rate_clk,
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);
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// only need one stage of synchronization in the simulator
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#[hdl]
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let rx_synchronized = reg_builder().clock_domain(cd).reset(true);
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connect(rx_synchronized, rx);
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#[hdl]
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let receiver = instance(receiver_no_queue());
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connect(receiver.cd, cd);
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connect(receiver.rx_synchronized, rx_synchronized);
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connect(output_byte, receiver.output_byte);
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#[hdl]
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let clock_gen = instance(uart_clock_gen(clock_input_properties(), BAUD_RATE));
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connect(clock_gen.cd, cd);
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connect(receiver.tick, clock_gen.tick);
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}
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#[test]
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#[hdl]
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fn test_receiver_no_queue_and_uart_clock_gen() {
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let _n = SourceLocation::normalize_files_for_tests();
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let text = "Testing 123, testing, testing.\n".intern();
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let m = receiver_no_queue_and_uart_clock_gen(text);
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let mut sim = Simulation::new(m);
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let writer = RcWriter::default();
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sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
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struct DumpVcdOnDrop {
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writer: Option<RcWriter>,
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}
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impl Drop for DumpVcdOnDrop {
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fn drop(&mut self) {
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if let Some(mut writer) = self.writer.take() {
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let vcd = String::from_utf8(writer.take()).unwrap();
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println!("####### VCD:\n{vcd}\n#######");
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}
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}
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}
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let mut writer = DumpVcdOnDrop {
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writer: Some(writer),
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};
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sim.write_clock(sim.io().cd.clk, false);
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sim.write_reset(sim.io().cd.rst, true);
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let mut received_text = String::new();
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for _cycle in 0..10000 {
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sim.advance_time(CLOCK_HALF_PERIOD);
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sim.write_clock(sim.io().cd.clk, true);
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sim.advance_time(CLOCK_HALF_PERIOD);
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sim.write_clock(sim.io().cd.clk, false);
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sim.write_reset(sim.io().cd.rst, false);
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#[hdl(sim)]
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if let HdlSome(byte) = sim.read(sim.io().output_byte) {
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let byte = byte.as_int();
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let expected_byte = sim.read(sim.io().cur_byte).as_int();
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assert_eq!(
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byte, expected_byte,
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"byte={:#x} {:?}, expected_byte={:#x} {:?}",
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byte, byte as char, expected_byte, expected_byte as char,
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);
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assert!(byte.is_ascii());
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received_text.push(byte as char);
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}
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}
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println!("{received_text:?}");
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assert!(received_text.len() >= text.len());
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let mut expected_text = text.repeat(received_text.len().div_ceil(text.len()));
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expected_text.truncate(received_text.len());
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assert_eq!(received_text, expected_text);
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let vcd = String::from_utf8(writer.writer.take().unwrap().take()).unwrap();
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println!("####### VCD:\n{vcd}\n#######");
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if vcd != include_str!("expected/receiver_no_queue_and_uart_clock_gen.vcd") {
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panic!();
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}
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}
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// TODO: test receiver()
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// TODO: test simple_uart()
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