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dynamic_part_select	Add torture test for (* nowrshmsk *) stride optimization	2024-01-10 20:28:36 +01:00
.gitignore
abc9.v
abc9.ys	abc9: uniquify blackboxes like whiteboxes (#2695)	2021-03-29 22:02:06 -07:00
aiger_dff.ys
async.sh
async.v
attrib05_port_conn.v
attrib05_port_conn.ys
attrib07_func_call.v
attrib07_func_call.ys	Moved tests that fail with Icarus Verilog to /tests/various. Those tests are just for parsing Verilog.	2019-06-04 10:42:42 +02:00
autoname.ys
blackbox_wb.ys
box_derive.ys
bug1496.ys	Fix #1496.	2019-11-18 04:16:48 +01:00
bug1531.ys
bug1614.ys
bug1710.ys	ast: fixes #1710; do not generate RTLIL for unreachable ternary	2020-02-27 16:55:55 -08:00
bug1745.ys
bug1781.ys
bug1876.ys	tests: add testcases from #1876	2020-04-14 12:39:10 -07:00
bug2014.ys	test: add test for #2014	2020-05-02 14:22:37 -07:00
bug3462.ys
bug4082.ys
cellarray_array_connections.ys
celledges_shift.ys
check.ys
check_2.ys
check_3.ys	check: Rephrase regex for portability	2024-03-11 10:45:17 +01:00
check_4.ys	celledges: Add read ports arst paths	2024-03-11 10:45:17 +01:00
chformal_check.ys
chformal_coverenable.ys
chparam.sh
clk2fflogic_effects.sh
clk2fflogic_effects.sv
const_arg_loop.sv
const_arg_loop.ys
const_func.sv
const_func.ys
const_func_block_var.v
const_func_block_var.ys
constant_drive_conflict.ys	check: Also check for conflicts with constant drivers	2023-06-23 18:07:28 +02:00
constcomment.ys
constmsk_test.v	Added tests/various/constmsk_test.ys	2014-09-04 15:07:30 +02:00
constmsk_test.ys
constmsk_testmap.v
countbits.sv
countbits.ys
deminout_unused.ys
design.ys
design1.ys	design: add test	2020-04-16 12:48:40 -07:00
design2.ys
dynamic_part_select.ys	Add torture test for (* nowrshmsk *) stride optimization	2024-01-10 20:28:36 +01:00
elab_sys_tasks.sv	Initial implementation of elaboration system tasks	2019-05-03 03:10:43 +03:00
elab_sys_tasks.ys
equiv_make_make_assert.ys
equiv_opt_multiclock.ys
equiv_opt_undef.ys	equiv_induct: Fix up assumption for $equiv cells in -undef mode.	2020-07-27 18:36:13 +02:00
exec.ys
fib.v
fib.ys
fib_tern.v	verilog: support recursive functions using ternary expressions	2021-02-12 14:43:42 -05:00
fib_tern.ys
func_port_implied_dir.sv
func_port_implied_dir.ys
gen_if_null.v
gen_if_null.ys
global_scope.ys
gzip_verilog.v.gz
gzip_verilog.ys
help.ys	tests: Fix invocation of 'help -cells'	2023-07-10 12:42:09 +02:00
hierarchy.sh
hierarchy_defer.ys	Expand test with `hierarchy' without -auto-top	2019-09-03 12:17:26 -07:00
hierarchy_generate.ys
hierarchy_param.ys
ice40_mince_abc9.ys	Add test for abc9+mince issue	2020-03-20 20:35:28 +00:00
integer_range_bad_syntax.ys
integer_real_bad_syntax.ys
json_escape_chars.ys	fix handling of escaped chars in json backend and frontend	2022-02-18 17:13:09 +01:00
logger_error.ys
logger_fail.sh
logger_nowarning.ys
logger_warn.ys
logger_warning.ys	Added back tests for logger	2020-03-13 15:00:18 +01:00
logic_param_simple.ys
mem2reg.ys
memory_word_as_index.data
memory_word_as_index.v
memory_word_as_index.ys
muxcover.ys
muxpack.v
muxpack.ys	More deadname stuff	2021-06-09 12:40:33 +02:00
param_struct.ys
peepopt.ys
plugin.cc
plugin.sh	tests: use yosys-config --datdir instead of hard-coded	2020-04-22 08:29:45 -07:00
pmgen_reduce.ys
pmux2shiftx.v	Cleanup tests	2020-02-27 10:17:29 -08:00
pmux2shiftx.ys	Add #1135 testcase	2019-06-27 11:02:52 -07:00
port_sign_extend.v
port_sign_extend.ys
primitives.ys	tests: add tests for primitives' src	2020-05-04 10:21:47 -07:00
printattr.ys
rand_const.sv
rand_const.ys
reg_wire_error.sv
reg_wire_error.ys
rename_scramble_name.ys
rtlil_z_bits.ys
run-test.sh
scopeinfo.ys
scratchpad.ys
script.ys
sformatf.ys	ast: use new format string helpers.	2023-08-11 04:46:52 +02:00
shregmap.v	tests: fix some test warnings	2020-05-25 10:07:58 -07:00
shregmap.ys
signed.ys
signext.ys
sim_const.ys	sim: Fix handling of constant-connected cell inputs at startup	2020-04-21 08:58:52 +01:00
specify.v
specify.ys
src.ys
sta.ys
struct_access.sv	Fix access to whole sub-structs (#3086)	2022-02-14 14:34:20 +01:00
struct_access.ys
sub.v	Add test for bug 3462	2022-08-29 10:10:09 +02:00
submod.ys
submod_extract.ys
sv_defines.ys
sv_defines_dup.ys
sv_defines_mismatch.ys
sv_defines_too_few.ys	Add support for SystemVerilog-style `define to Verilog frontend	2020-03-27 16:08:26 +00:00
sv_implicit_ports.sh
svalways.sh
wreduce.ys
write_gzip.ys
xaiger.ys