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https://github.com/YosysHQ/yosys
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38 lines
769 B
Plaintext
38 lines
769 B
Plaintext
read_verilog <<EOF
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(* whitebox *)
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(* final_name=$sformatf("aa%d", X) *)
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module aa(input wire d, output wire q);
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parameter [1:0] X = 0;
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assign q = X[d];
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endmodule
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(* whitebox *)
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(* final_name=$sformatf("bb%d", X) *)
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module bb(input wire d, output wire q);
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parameter [1:0] X = 0;
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assign q = X[~d];
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endmodule
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(* whitebox *)
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(* final_name=$sformatf("cc%d", X) *)
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module cc(input wire d, output wire q);
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parameter [1:0] X = 0;
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assign q = ~X[d];
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endmodule
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module top;
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wire d, q1, q2, q3, q3, q4, q5, q6;
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aa #(.X(1)) aa1(.d(d), .q(q1));
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aa #(.X(2)) aa2(.d(d), .q(q2));
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bb #(.X(1)) bb1(.d(d), .q(q3));
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bb #(.X(3)) bb2(.d(d), .q(q4));
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cc #(.X(1)) cc1(.d(d), .q(q5));
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cc #(.X(1)) cc2(.d(d), .q(q6));
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endmodule
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EOF
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box_derive -naming_attr final_name top
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