Akash Levy
2f8c9327b3
Verific: guard large-mem RAM width/word-count against int overflow
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Address review feedback on the large-memory fix:
- comment explaining the 64-bit promotion and the remaining int limits
- log_error if the per-word width or word count would overflow RTLIL's
int memory->width / memory->size fields, instead of silently truncating
Co-authored-by: Cursor <cursoragent@cursor.com>
2026-06-24 23:33:55 -07:00
Akash Levy
2c790e52cd
Large mem fix with long long
2026-06-24 17:21:10 -07:00
Mohamed Gaber
d986ee91ac
CMake: integrate silimate additions and extensions
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- update CMakeLists.txt to load two new files:
- SilimateConfig.cmake: sets Silimate configuration options and defaults
- SilimateVerific.cmake: compiles Verific library, optionally with Silimate modifications
- include silimate tests in test Makefile
2026-06-10 20:27:52 +03:00
Mohamed Gaber
e58125b605
Merge remote-tracking branch 'upstream/main' into silimate
2026-06-09 16:22:51 +03:00
Miodrag Milanović
693d5a7eb0
Merge pull request #5903 from YosysHQ/krys/verific_memsize
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verific: Fix non-contiguous memory flattening producing out of bounds accesses in some cases
2026-06-04 05:43:04 +00:00
Miodrag Milanovic
ce280354cf
Update CI scripts for CMake
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Co-authored-by: Catherine <whitequark@whitequark.org>
2026-06-03 08:58:11 +00:00
Catherine
a727e7f6e7
Migrate build system to CMake
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See #5895 for details.
This commit does not include CI or documentation changes.
2026-06-03 08:58:10 +00:00
Krystine Sherwin
5f53410db7
verific: Fix negative array dimensions
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Recurse over memory dimensions once, doing both our min/max address checking and parsing out the initval. This also avoids problems with negative numbers (if `a < b` and one or both are negative, `a` might be the intended `max_addr_chunk`).
Fix sub addressing, where we use some but not all of the current dimension's bits.
2026-05-29 18:40:25 +12:00
Krystine Sherwin
21966ef496
verific: Fix non-contiguous memory init
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Recurse over nested type ranges to calculate true addresses.
2026-05-29 18:40:25 +12:00
Krystine Sherwin
099c664dc9
verific: Fix upto ranges
2026-05-29 18:40:23 +12:00
Krystine Sherwin
7cf0c55466
verific: Fix non-contiguous memory flattening
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May not be the best approach, insofar as it uses empty memory elements for padding out the alignment, but it does avoid costly address arithmetic.
Still needs to adjust ascii init val addresses, but should work fine for read/write accesses.
2026-05-29 18:40:23 +12:00
Miodrag Milanovic
8bbc3c359c
Remove id2cstr uses in our code base
2026-05-16 19:49:45 +02:00
Codexplorer
e41b969da2
Refactored uses of log_id()
2026-05-08 20:59:24 -07:00
Akash Levy
e1aade6a1f
Update frontends/verific/verific.cc
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Co-authored-by: greptile-apps[bot] <165735046+greptile-apps[bot]@users.noreply.github.com>
2026-04-30 14:15:44 -07:00
Akash Levy
89a8250ae8
Update frontends/verific/verific.cc
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Co-authored-by: greptile-apps[bot] <165735046+greptile-apps[bot]@users.noreply.github.com>
2026-04-30 14:15:25 -07:00
Akash Levy
4d110a96bf
Localize external package/global net
2026-04-30 10:51:03 -07:00
Stan Lee
489fb6ea54
compilation err
2026-04-28 16:22:12 -07:00
Stan Lee
18dc5cc2cc
remove pointer
2026-04-28 16:21:23 -07:00
Stan Lee
48329bd36a
change to string for consistency
2026-04-28 16:20:00 -07:00
Stan Lee
6f5b52807c
whitespace
2026-04-28 16:18:36 -07:00
Stan Lee
dd6e440937
rename and clean
2026-04-28 16:16:57 -07:00
Stan Lee
e801ea4fdb
delete module frontend
2026-04-28 15:12:50 -07:00
Akash Levy
bf40364bd0
No operator optimization, but it passes all tests
2026-04-22 03:12:26 -07:00
Akash Levy
89d56882ba
Pullup/pulldown primitives
2026-04-15 12:37:18 -07:00
Abhinav Tondapu
0f641f70b2
adding comments
2026-04-02 15:30:45 -07:00
Abhinav Tondapu
1f96d3209b
[ENG-1842] adding file dump from verific
2026-04-02 09:54:26 -07:00
Abhinav Tondapu
d5122ed2fa
[ENG-1827] ignore placeholder/empty ports from verific
2026-03-27 15:20:12 -07:00
Akash Levy
bf4ce9d6f7
Import uniquify fix
2026-02-19 00:24:32 -08:00
Akash Levy
807df40422
Undo the weird abc changes
2026-02-03 23:21:48 -08:00
Akash Levy
8e5d24aa6b
Bump yosys to latest
2026-02-03 06:08:36 -08:00
Sean Luchen
224549fb88
Guard vhdl_file::UNDEFINED behind VERIFIC_VHDL_SUPPORT.
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Signed-off-by: Sean Luchen <seanluchen@google.com>
2026-02-02 15:26:03 -08:00
Akash Levy
7c70026610
Fix verific issue
2026-02-01 00:16:10 -08:00
Akash Levy
bdc9ad9f53
Bump version
2026-01-30 19:29:00 -08:00
Akash Levy
a9cf998f9f
Merge from upstream
2026-01-29 17:46:44 -08:00
Miodrag Milanovic
b70f527c67
verific: fixed -sv2017 option and added ability to set VHDL standard if applicable
2026-01-29 10:32:30 +01:00
Natalia
8d504ecb48
verific: use MFCU for SV file list
2026-01-29 00:03:28 -08:00
Natalia
188082551a
verific: only use MFCU when VHDL present
2026-01-28 03:37:08 -08:00
nataliakokoromyti
f3c87610f5
verific: allow mixed SV/VHDL in -f files
2026-01-24 23:46:45 -08:00
Akash Levy
b11037e6c6
Merge remote-tracking branch 'upstream/main'
2026-01-21 15:13:57 -08:00
Miodrag Milanovic
d0fa4781c6
verific: Fix -sv2017 message and formatting
2026-01-20 08:07:26 +01:00
Miodrag Milanovic
cc3038f468
verific: Fix -sv2017 message
2026-01-19 16:32:46 +01:00
Miodrag Milanovic
d095d2c405
verific: add explicit System Verilog 2017 option
2026-01-16 07:56:53 +01:00
Akash Levy
1941e8f042
Bump yosys and abc to latest
2025-12-25 03:46:16 -05:00
N. Engelhardt
45d654e2d7
avoid merging formal properties
2025-12-17 20:25:24 +01:00
Akash Levy
76c12f8f8c
Merge branch 'YosysHQ:main' into main
2025-11-03 13:38:04 -05:00
Mohamed Gaber
dec28f65ae
Merge remote-tracking branch 'donn/pyosys_bugfixes' into merge_pybind11
2025-10-26 02:39:43 +03:00
Robert O'Callahan
25aafab86b
Set port_id for Verific PortBus wires
2025-10-23 20:51:53 +00:00
Miodrag Milanovic
1f11b2c529
verific: Add src to message missed in #5406
2025-10-13 15:16:17 +02:00
Miodrag Milanovic
dc959cdf4a
verific: Fix error compiling without VERIFIC_LINEFILE_INCLUDES_COLUMNS
2025-10-13 15:16:17 +02:00
Miodrag Milanovic
9570b39519
verifix: fix bits() deprecation warnings
2025-10-13 09:57:22 +02:00
