Address review feedback on the large-memory fix:
- comment explaining the 64-bit promotion and the remaining int limits
- log_error if the per-word width or word count would overflow RTLIL's
int memory->width / memory->size fields, instead of silently truncating
Co-authored-by: Cursor <cursoragent@cursor.com>
- update CMakeLists.txt to load two new files:
- SilimateConfig.cmake: sets Silimate configuration options and defaults
- SilimateVerific.cmake: compiles Verific library, optionally with Silimate modifications
- include silimate tests in test Makefile
Recurse over memory dimensions once, doing both our min/max address checking and parsing out the initval. This also avoids problems with negative numbers (if `a < b` and one or both are negative, `a` might be the intended `max_addr_chunk`).
Fix sub addressing, where we use some but not all of the current dimension's bits.
May not be the best approach, insofar as it uses empty memory elements for padding out the alignment, but it does avoid costly address arithmetic.
Still needs to adjust ascii init val addresses, but should work fine for read/write accesses.
Patch by Ruben Undheim via the Debian project. The patch originated
as 0009-Some-spelling-errors-fixed.patch and was dated 2018-07-12
there.
See also issue #5805.
This commit adds support for SystemVerilog array-to-array assignment
operations that were previously unsupported:
1. Direct array assignment: `b = a;`
2. Array ternary expressions: `out = sel ? a : b;`
Both single-dimensional and multi-dimensional unpacked arrays are
supported. The implementation expands these array operations during
AST simplification into element-wise assignments.
Example of now-supported syntax:
```systemverilog
wire [7:0] state_regs[8];
wire [7:0] r[8];
wire [7:0] sel[8];
assign sel = condition ? state_regs : r;
```
Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
