2471 commits

Author	SHA1	Message	Date
Clifford Wolf	eb67a7532b	Add $allconst and $allseq cell types ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-02-23 13:14:47 +01:00
Robert Ou	2abcd98527	coolrunner2: Move LOC attributes onto the IO cells	2018-01-17 16:17:32 -08:00
Clifford Wolf	9ac560f5d3	Add "dffinit -highlow" and fix synth_intel ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-01-09 18:42:19 +01:00
Clifford Wolf	b66d50e62d	Fix minor typo in "prep" help message	2017-12-19 21:44:05 +01:00
Graham Edgecombe	f93e6637aa	Fix port names in SB_IO_OD	2017-12-10 15:33:38 +00:00
Graham Edgecombe	52ace35a73	Remove trailing comma from SB_IO_OD port list ... This isn't compatible with Icarus Verilog.	2017-12-10 15:33:38 +00:00
Tim Ansell	3cc31f197c	Fix spelling in -vpr help for synth_ice40	2017-12-08 18:44:45 -08:00
Clifford Wolf	1f6e8f86c5	Merge pull request #462 from daveshah1/up5k ... Add remaining UltraPlus cells to ice40 techlib	2017-11-28 15:53:53 +01:00
David Shah	5e8d1922a4	Add remaining UltraPlus cells to ice40 techlib	2017-11-28 11:07:49 +00:00
Clifford Wolf	4782d59a3f	Merge pull request #455 from daveshah1/up5k ... Add UltraPlus specific cells to ice40 techlib	2017-11-18 19:12:48 +01:00
David Shah	0505f1043c	Remove unnecessary keep attributes	2017-11-18 17:53:21 +00:00
Clifford Wolf	c01df04e32	Merge pull request #453 from dh73/master ... Updating Intel FPGA subsystem with Cyclone 10, minor changes in examples/intel directory and Speedster cells	2017-11-18 09:56:36 +01:00
David Shah	8ae73e60e2	Merge branch 'master' into up5k	2017-11-17 15:15:39 +00:00
Clifford Wolf	234726c655	Add "synth_ice40 -vpr"	2017-11-16 21:37:02 +01:00
David Shah	f9f3ca5da0	Add some UltraPlus cells to ice40 techlib	2017-11-16 12:24:35 +00:00
dh73	3fd1d61e2a	Initial Cyclone 10 support	2017-11-08 22:45:21 -06:00
dh73	1fc061d90c	Organizing Speedster file names	2017-11-08 20:23:55 -06:00
Larry Doolittle	50bcd9a728	Clean whitespace and permissions in techlibs/intel	2017-10-05 16:23:49 +02:00
Clifford Wolf	65f91e5120	Rename "write_verilog -nobasenradix" to "write_verilog -decimal"	2017-10-03 17:31:21 +02:00
dh73	4718e65763	Tested and working altsyncarm without init files	2017-10-01 19:59:45 -05:00
dh73	cbaba62401	Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now	2017-10-01 11:04:17 -05:00
Clifford Wolf	c5b204d8d2	Add first draft of eASIC back-end	2017-09-29 17:53:43 +02:00
Clifford Wolf	e64b9d5a4d	Fix synth_ice40 doc regarding -top default	2017-09-29 17:52:57 +02:00
Andrew Zonenberg	122532b7e1	Added RESET_TO_MAX parameter to $__COUNT_ cell. Cannot yet be extracted.	2017-09-14 10:26:32 -07:00
Andrew Zonenberg	a84172b23b	Initial support for extraction of counters with clock enable	2017-09-14 10:26:10 -07:00
Clifford Wolf	2f75240e36	Merge pull request #406 from azonenberg/coolrunner-techmap ... Coolrunner techmapping improvements	2017-09-02 13:43:51 +02:00
Robert Ou	5f65e24ccb	coolrunner2: Finish fixing special-use p-terms	2017-09-01 07:22:16 -07:00
Robert Ou	fa04366f38	coolrunner2: Generate a feed-through AND term when necessary	2017-09-01 07:22:01 -07:00
Robert Ou	6775177171	coolrunner2: Initial fixes for special p-terms ... Certain signals can only be controlled by a product term and not a sum-of-products. Do the initial work for fixing this.	2017-09-01 07:21:51 -07:00
Robert Ou	7f08be4304	coolrunner2: Fix mapping of flip-flops	2017-09-01 07:21:39 -07:00
Robert Ou	ac84f47829	coolrunner2: Combine some for loops together	2017-09-01 07:21:31 -07:00
Andrew Zonenberg	40021d2fd8	Fixed typo in error message	2017-09-01 06:45:10 -07:00
Andrew Zonenberg	fc0c7f74dc	Added blackbox $__COUNT_ cell model	2017-09-01 06:44:28 -07:00
Andrew Zonenberg	80aaf50302	Refactoring: moved modules still in cells_sim to cells_sim_wip	2017-09-01 06:44:15 -07:00
Andrew Zonenberg	06754108fc	Merge branch 'master' of https://github.com/cliffordwolf/yosys into counter-extraction	2017-08-30 16:40:41 -07:00
Andrew Zonenberg	634f18be96	extract_counter: Minor changes requested to comply with upstream policy, fixed a few typos	2017-08-30 16:28:25 -07:00
Andrew Zonenberg	3fc1b9f3fd	Finished refactoring counter extraction to be nice and generic. Implemented techmapping from $__COUNT_ to GP_COUNTx cells.	2017-08-28 22:18:57 -07:00
Andrew Zonenberg	b5c15636c5	Refactoring: Renamed greenpak4_counters pass to extract_counter, moved it to techmap/ since it's going to become a generic pass	2017-08-28 22:18:34 -07:00
Andrew Zonenberg	c3145863e7	Reformatted GP_COUNTx_ADV resets to avoid Yosys thinking that they're multi-edge-sensitive and getting confused.	2017-08-28 14:25:46 -07:00
Andrew Zonenberg	e62362225c	Fixed bug causing GP_SPI model to not synthesize	2017-08-27 07:31:48 -07:00
Andrew Zonenberg	e6eaf487b6	Fixed more issues with GreenPAK counter sim models	2017-08-15 09:18:36 -07:00
Andrew Zonenberg	3a404be62a	Updated PGEN model to have level triggered reset (matches actual hardware behavior	2017-08-15 09:18:27 -07:00
Andrew Zonenberg	e5109847c9	Fixed bug in GP_COUNTx model	2017-08-15 09:18:17 -07:00
Andrew Zonenberg	66b256d40e	Fixed bug where GP_COUNTx_ADV would wrap even when KEEP was high	2017-08-15 09:18:07 -07:00
Clifford Wolf	2cf0b5c157	Merge pull request #381 from azonenberg/countfix ... Added better behavioral models for GreenPAK counters. Refactored cells_sim into two files so analog/mixed signal stuff is separate	2017-08-14 21:47:26 +02:00
Robert Ou	78fd24f40f	coolrunner2: Add INVERT parameter to some BUFGs	2017-08-14 12:13:33 -07:00
Robert Ou	1e3ffd57cb	coolrunner2: Add FFs with clock enable to cells_sim.v	2017-08-14 12:13:25 -07:00
Andrew Zonenberg	348acbd968	Fixed typo in GP_COUNT8 sim model	2017-08-14 10:45:40 -07:00
Andrew Zonenberg	c205d571df	Fixed typo in error message	2017-08-14 10:45:40 -07:00
Andrew Zonenberg	0a6c702c41	Changed LEVEL resets for GP_COUNTx to be properly synthesizeable	2017-08-14 10:45:40 -07:00