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https://github.com/YosysHQ/yosys
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Initial support for extraction of counters with clock enable
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parent
c4a70a8cc3
commit
a84172b23b
2 changed files with 131 additions and 30 deletions
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@ -161,8 +161,8 @@ module \$__COUNT_ (CE, CLK, OUT, POUT, RST, UP);
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parameter WIDTH = 8;
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parameter DIRECTION = "DOWN";
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//If we have a CE, or DIRECTION other than DOWN fail... GP_COUNTx_ADV is not supported yet
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if(HAS_CE || (DIRECTION != "DOWN") ) begin
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//If we have a DIRECTION other than DOWN fail... GP_COUNTx_ADV is not supported yet
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if(DIRECTION != "DOWN") begin
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initial begin
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$display("ERROR: \$__COUNT_ support for GP_COUNTx_ADV is not yet implemented. This counter should never have been extracted (bug in extract_counter pass?).");
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$finish;
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@ -187,28 +187,72 @@ module \$__COUNT_ (CE, CLK, OUT, POUT, RST, UP);
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//Looks like a legal counter! Do something with it
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else if(WIDTH <= 8) begin
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GP_COUNT8 #(
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.COUNT_TO(COUNT_TO),
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.RESET_MODE(RESET_MODE),
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.CLKIN_DIVIDE(1)
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) _TECHMAP_REPLACE_ (
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.CLK(CLK),
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.RST(RST),
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.OUT(OUT),
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.POUT(POUT)
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);
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if(HAS_CE) begin
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wire ce_not;
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GP_INV ceinv(
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.IN(CE),
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.OUT(ce_not)
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);
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GP_COUNT8_ADV #(
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.COUNT_TO(COUNT_TO),
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.RESET_MODE(RESET_MODE),
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.RESET_VALUE("COUNT_TO"),
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.CLKIN_DIVIDE(1)
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) _TECHMAP_REPLACE_ (
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.CLK(CLK),
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.RST(RST),
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.OUT(OUT),
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.UP(1'b0), //always count down for now
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.KEEP(ce_not),
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.POUT(POUT)
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);
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end
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else begin
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GP_COUNT8 #(
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.COUNT_TO(COUNT_TO),
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.RESET_MODE(RESET_MODE),
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.CLKIN_DIVIDE(1)
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) _TECHMAP_REPLACE_ (
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.CLK(CLK),
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.RST(RST),
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.OUT(OUT),
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.POUT(POUT)
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);
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end
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end
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else begin
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GP_COUNT14 #(
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.COUNT_TO(COUNT_TO),
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.RESET_MODE(RESET_MODE),
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.CLKIN_DIVIDE(1)
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) _TECHMAP_REPLACE_ (
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.CLK(CLK),
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.RST(RST),
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.OUT(OUT)
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);
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if(HAS_CE) begin
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wire ce_not;
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GP_INV ceinv(
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.IN(CE),
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.OUT(ce_not)
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);
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GP_COUNT14_ADV #(
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.COUNT_TO(COUNT_TO),
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.RESET_MODE(RESET_MODE),
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.RESET_VALUE("COUNT_TO"),
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.CLKIN_DIVIDE(1)
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) _TECHMAP_REPLACE_ (
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.CLK(CLK),
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.RST(RST),
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.OUT(OUT),
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.UP(1'b0), //always count down for now
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.KEEP(ce_not),
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.POUT(POUT)
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);
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end
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else begin
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GP_COUNT14 #(
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.COUNT_TO(COUNT_TO),
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.RESET_MODE(RESET_MODE),
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.CLKIN_DIVIDE(1)
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) _TECHMAP_REPLACE_ (
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.CLK(CLK),
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.RST(RST),
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.OUT(OUT)
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);
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end
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end
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endmodule
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