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Author SHA1 Message Date
Eddie Hung
6d4b6b1e69
Merge pull request #1575 from rodrigomelo9/master 
Fixed some missing "verilog_" in documentation
 2019-12-15 19:00:34 -08:00
Eddie Hung
b0231df3e5
Merge pull request #1577 from gromero/for-yosys 
manual: Fix text in Abstract section
 2019-12-15 18:59:55 -08:00
Eddie Hung
b1555fa32c
Merge pull request #1578 from noopwafel/eqneq-debug 
Fix opt_expr.eqneq.cmpzero debug print
 2019-12-15 18:59:36 -08:00
Alyssa Milburn
e709fd3da1 Fix opt_expr.eqneq.cmpzero debug print 2019-12-15 20:40:38 +01:00
Eddie Hung
c0339bbbf1 Name inputs/outputs of aiger 'i%d' and 'o%d' 2019-12-13 16:21:09 -08:00
Diego H
266993408a Refactoring memory attribute matching based on IEEE 1364.1 and Tool specific 2019-12-13 15:43:24 -06:00
Eddie Hung
52875b0d61
Merge pull request #1533 from dh73/bram_xilinx 
Adjust Xilinx xc7/xcu BRAM min bits threshold for RAMB18E1
 2019-12-13 12:01:03 -08:00
Eddie Hung
a5764a1236 Disable RAM16X1D test 2019-12-13 10:28:13 -08:00
Eddie Hung
83d36394f8 opt_merge to discard \init of '$' cells with 'Q' port when merging 2019-12-13 10:26:37 -08:00
Eddie Hung
d86d073ad6 Add testcase 2019-12-13 10:26:30 -08:00
Eddie Hung
c3262d6075 Disable RAM16X1D match rule; carry-over from LUT4 arches 2019-12-13 08:59:17 -08:00
Eddie Hung
d6514fc2e1 RAM64M8 to also have [5:0] for address 2019-12-13 08:54:19 -08:00
Eddie Hung
dd7d2d8db6 Duplicate tribuf call, credit to @mwkmwkmwk 2019-12-13 08:51:05 -08:00
Diego H
1c96345587 Renaming BRAM memory tests for the sake of uniformity 2019-12-13 09:33:18 -06:00
Rodrigo Alejandro Melo
e9dc2759c4 Fixed some missing "verilog_" in documentation 2019-12-13 10:17:05 -03:00
N. Engelhardt
91f427d719 check scratchpad variables for custom abc scripts 2019-12-13 12:54:52 +01:00
N. Engelhardt
ce3615b367 add periods and newlines to help message 2019-12-13 10:28:34 +01:00
Eddie Hung
d0ee4cd88f Remove extraneous synth_xilinx call 2019-12-12 19:00:26 -08:00
Eddie Hung
01116f0f0a Add tests for these new models 2019-12-12 18:52:48 -08:00
Eddie Hung
8925bf4b96 Add RAM32X6SDP and RAM64X3SDP modes 2019-12-12 18:52:28 -08:00
Eddie Hung
50e0c83560 Fix RAM64M model to have 6 bit address bus 2019-12-12 18:52:03 -08:00
Eddie Hung
037d1a03df Add #1460 testcase 2019-12-12 17:49:55 -08:00
Eddie Hung
7a9d1be97d Add memory rules for RAM16X1D, RAM32M, RAM64M 2019-12-12 17:44:59 -08:00
Eddie Hung
caab66111e Rename memory tests to lutram, add more xilinx tests 2019-12-12 17:44:37 -08:00
Diego H
751a18d7e9 Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1 test. 2019-12-12 17:32:58 -06:00
Eddie Hung
fce6bad6ae Remove 'clkpart' entry in CHANGELOG 2019-12-12 15:02:46 -08:00
Eddie Hung
bea15b537b Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-12 14:57:17 -08:00
Eddie Hung
9ab1feeaf1 abc9_map.v: fix Xilinx LUTRAM 2019-12-12 14:56:52 -08:00
Eddie Hung
3eed8835b5 abc9_map.v: fix Xilinx LUTRAM 2019-12-12 14:56:15 -08:00
Eddie Hung
47ac1b01e6 Add test 2019-12-12 14:43:13 -08:00
Eddie Hung
3bd623bb05 synth_xilinx: error out if tristate without '-iopad' 2019-12-12 14:33:33 -08:00
Eddie Hung
abf99d4dae tribuf: set scratchpad boolean 'tribuf.added_something' 2019-12-12 14:32:29 -08:00
Diego H
e33f407655 Adding a note (TODO) in the memory_params.ys check file 2019-12-12 16:06:46 -06:00
N. Engelhardt
1187e91c2f add test and make help message more verbose 2019-12-12 20:51:59 +01:00
Diego H
937ec1ee78 Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1 2019-12-12 13:50:36 -06:00
Diego H
ab6ac8327f Merge https://github.com/YosysHQ/yosys into bram_xilinx 2019-12-12 13:40:05 -06:00
Eddie Hung
23fcfd0adb Make SV2017 compliant courtesy of @wsnyder 2019-12-12 07:34:07 -08:00
N. Engelhardt
4c7cda1c8b add a command to read/modify scratchpad contents 2019-12-12 16:25:03 +01:00
Eddie Hung
4a80510877 Even more obvious testcase 2019-12-11 23:52:05 -08:00
Eddie Hung
61a1f3f49b Make testcase clearer with \o having its own init 2019-12-11 23:48:09 -08:00
Eddie Hung
1ac1697e15 Stray log_dump 2019-12-11 16:59:00 -08:00
Eddie Hung
af36943cb9 Preserve size of $genval$-s in for loops 2019-12-11 16:52:37 -08:00
Eddie Hung
151f7533e8 Add testcase 2019-12-11 16:52:37 -08:00
Eddie Hung
2666482282 Update README.md :: abc_ -> abc9_ 2019-12-11 16:38:43 -08:00
Eddie Hung
f022645cd2 Fix bitwidth mismatch; suppresses iverilog warning 2019-12-11 13:02:07 -08:00
Eddie Hung
9a892199f7 Suppress warning message for init[i] = 1'bx 2019-12-11 11:27:10 -08:00
Eddie Hung
e75ca29b19 Add test: 'Warning: ignoring initial value on non-register: \o' 2019-12-11 11:26:54 -08:00
Gustavo Romero
993a77d19b manual: Fix text in Abstract section 2019-12-11 08:22:08 -03:00
David Shah
613334d9dc
Merge pull request #1564 from ZirconiumX/intel_housekeeping 
Intel housekeeping
 2019-12-11 08:46:10 +00:00
Dan Ravensloft
85a14895ca synth_intel: a10gx -> arria10gx 2019-12-10 13:48:10 +00:00