Eddie Hung
f022645cd2
Fix bitwidth mismatch; suppresses iverilog warning
2019-12-11 13:02:07 -08:00
David Shah
613334d9dc
Merge pull request #1564 from ZirconiumX/intel_housekeeping
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Intel housekeeping
2019-12-11 08:46:10 +00:00
Dan Ravensloft
85a14895ca
synth_intel: a10gx -> arria10gx
2019-12-10 13:48:10 +00:00
Dan Ravensloft
eab3272cde
synth_intel: cyclone10 -> cyclone10lp
2019-12-10 13:47:58 +00:00
Eddie Hung
7e5602ad17
Merge pull request #1545 from YosysHQ/eddie/ice40_wrapcarry_attr
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Preserve SB_CARRY name and attributes when using $__ICE40_CARRY_WRAPPER
2019-12-09 17:38:48 -08:00
Eddie Hung
fb203d2a2c
ice40_opt to restore attributes/name when unwrapping
2019-12-09 14:29:29 -08:00
Eddie Hung
36a88be609
ice40_wrapcarry -unwrap to preserve 'src' attribute
2019-12-09 14:28:54 -08:00
Eddie Hung
eff858cd33
unmap $__ICE40_CARRY_WRAPPER in test
2019-12-09 14:20:35 -08:00
Eddie Hung
bbdf2452b3
-unwrap to create $lut not SB_LUT4 for opt_lut
2019-12-09 13:27:09 -08:00
Eddie Hung
500ed9b501
Sensitive to direct inst of $__ICE40_CARRY_WRAPPER; recreate SB_LUT4
2019-12-09 12:45:22 -08:00
Eddie Hung
e05372778a
ice40_wrapcarry to really preserve attributes via -unwrap option
2019-12-09 11:48:28 -08:00
Eddie Hung
ecb0c68f07
Merge pull request #1555 from antmicro/fix-macc-xilinx-test
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tests: arch: xilinx: Change order of arguments in macc.sh
2019-12-06 23:04:04 -08:00
Eddie Hung
946d5854c0
Drop keep=0 attributes on SB_CARRY
2019-12-06 17:27:47 -08:00
Jan Kowalewski
dcb30b5f4a
tests: arch: xilinx: Change order of arguments in macc.sh
2019-12-06 09:15:49 +01:00
Clifford Wolf
7dece7955e
Merge pull request #1551 from whitequark/manual-cell-operands
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Clarify semantics of comb cells, in particular shifts
2019-12-05 08:24:24 -08:00
Eddie Hung
a7e0cca480
Merge SB_CARRY+SB_LUT4's attributes when creating $__ICE40_CARRY_WRAPPER
2019-12-05 07:01:18 -08:00
Eddie Hung
d8fbf88980
Add WIP test for unwrapping $__ICE40_CARRY_WRAPPER
2019-12-05 07:01:02 -08:00
whitequark
e97e33d00d
kernel: require \B_SIGNED=0 on $shl, $sshl, $shr, $sshr.
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Before this commit, these cells would accept any \B_SIGNED and in
case of \B_SIGNED=1, would still treat the \B input as unsigned.
Also fix the Verilog frontend to never emit such constructs.
2019-12-04 11:59:36 +00:00
whitequark
ec4c9267b3
manual: document behavior of many comb cells more precisely.
2019-12-04 11:32:14 +00:00
Marcin Kościelnicki
fcce94010f
xilinx: Add tristate buffer mapping. ( #1528 )
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Fixes #1225 .
2019-12-04 09:44:00 +01:00
Marcin Kościelnicki
2abe38e73e
iopadmap: Refactor and fix tristate buffer mapping. ( #1527 )
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The previous code for rerouting wires when inserting tristate buffers
was overcomplicated and didn't handle all cases correctly (in
particular, only cell connections were rewired — internal connections
were not).
2019-12-04 08:44:08 +01:00
Marcin Kościelnicki
10014e2643
xilinx: Add models for LUTRAM cells. ( #1537 )
2019-12-04 06:31:09 +01:00
Eddie Hung
67f1ce2d43
Check SB_CARRY name also preserved
2019-12-03 14:51:39 -08:00
Eddie Hung
ed3f359175
$__ICE40_CARRY_WRAPPER to use _TECHMAP_REPLACE_ for SB_CARRY to preserve
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name and attr
2019-12-03 14:49:10 -08:00
Eddie Hung
1ea9ce0ad7
ice40_opt to ignore (* keep *) -ed cells
2019-12-03 14:48:39 -08:00
Eddie Hung
5897b918b3
ice40_wrapcarry to preserve SB_CARRY's attributes
2019-12-03 14:48:11 -08:00
Eddie Hung
8de17877d4
Add testcase
2019-12-03 14:48:00 -08:00
Clifford Wolf
2ec6d832dc
Merge pull request #1524 from pepijndevos/gowindffinit
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Gowin: add and test DFF init values
2019-12-03 08:43:18 -08:00
Pepijn de Vos
a7d34a7cb5
update test
2019-12-03 16:56:15 +01:00
Pepijn de Vos
a3b25b4af8
Use -match-init to not synth contradicting init values
2019-12-03 15:12:25 +01:00
David Shah
7f35b2ff62
Merge pull request #1542 from YosysHQ/dave/abc9-loop-fix
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abc9: Fix breaking of SCCs
2019-12-02 10:20:21 +00:00
Clifford Wolf
cacf870d85
Merge pull request #1539 from YosysHQ/mwk/ilang-bounds-check
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read_ilang: do bounds checking on bit indices
2019-12-01 16:30:48 -08:00
David Shah
e9ce4e658b
abc9: Fix breaking of SCCs
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Signed-off-by: David Shah <dave@ds0.me>
2019-12-01 20:44:56 +00:00
Miodrag Milanović
5f4c35c753
Merge pull request #1540 from YosysHQ/mwk/xilinx-bufpll
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xilinx: Add missing blackbox cell for BUFPLL.
2019-11-29 17:33:41 +01:00
Marcin Kościelnicki
2badaa9adb
xilinx: Add missing blackbox cell for BUFPLL.
2019-11-29 16:56:27 +01:00
Eddie Hung
419ca5c207
Revert "Fold loop"
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This reverts commit a30d5e1cc3
2019-11-27 21:55:56 -08:00
Marcin Kościelnicki
0ce22cea46
read_ilang: do bounds checking on bit indices
2019-11-27 22:24:39 +01:00
Eddie Hung
6464dc35ec
Merge pull request #1536 from YosysHQ/eddie/xilinx_dsp_muladd
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xilinx_dsp: consider sign and zero-extension when packing post-multiplier adder
2019-11-27 08:00:22 -08:00
Clifford Wolf
41e0ddf4f4
Merge pull request #1501 from YosysHQ/dave/mem_copy_attr
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memory_collect: Copy attr from RTLIL::Memory to cell
2019-11-27 11:25:23 +01:00
Clifford Wolf
f43c0bd8ba
Merge pull request #1534 from YosysHQ/mwk/opt_share-fix
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opt_share: Fix handling of fine cells.
2019-11-27 11:23:16 +01:00
Eddie Hung
95053d9010
Merge pull request #1535 from YosysHQ/eddie/write_xaiger_improve
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write_xaiger improvements
2019-11-27 01:04:29 -08:00
Eddie Hung
de3476cc23
No need for -abc9
2019-11-26 23:08:14 -08:00
Marcin Kościelnicki
fdcbda195b
opt_share: Fix handling of fine cells.
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Fixes #1525 .
2019-11-27 08:01:07 +01:00
Eddie Hung
5e67df38ed
latch -> box
2019-11-26 22:59:05 -08:00
Eddie Hung
4a0198128e
Add citation
2019-11-26 22:51:16 -08:00
Eddie Hung
2105ae176a
Check for either sign or zero extension for postAdd packing
2019-11-26 22:51:00 -08:00
Eddie Hung
15042eaf57
Remove notes
2019-11-26 22:41:35 -08:00
Eddie Hung
a30d5e1cc3
Fold loop
2019-11-26 21:57:50 -08:00
Eddie Hung
68717dd03b
Do not sigmap keep bits inside write_xaiger
2019-11-26 21:57:50 -08:00
Eddie Hung
7136cee6b4
xaiger: do not promote output wires
2019-11-26 21:55:37 -08:00
