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Merge pull request #1540 from YosysHQ/mwk/xilinx-bufpll

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xilinx: Add missing blackbox cell for BUFPLL.
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Miodrag Milanović 2019-11-29 17:33:41 +01:00 • committed by GitHub
commit 5f4c35c753
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2 changed files with 21 additions and 0 deletions
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1
techlibs/xilinx/cells_xtra.py
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@ -372,6 +372,7 @@ CELLS = [
Cell('BUFIO2', port_attrs={'IOCLK': ['clkbuf_driver'], 'DIVCLK': ['clkbuf_driver']}),
Cell('BUFIO2_2CLK', port_attrs={'IOCLK': ['clkbuf_driver'], 'DIVCLK': ['clkbuf_driver']}),
Cell('BUFIO2FB', port_attrs={'O': ['clkbuf_driver']}),
Cell('BUFPLL', port_attrs={'IOCLK': ['clkbuf_driver']}),
Cell('BUFPLL_MCB', port_attrs={'IOCLK0': ['clkbuf_driver'], 'IOCLK1': ['clkbuf_driver']}),
# Clock buffers (IO and regional) -- Virtex.

20
techlibs/xilinx/cells_xtra.v
View file

@ -5240,9 +5240,13 @@ module RAMB18E1 (...);
parameter IS_RSTRAMB_INVERTED = 1'b0;
parameter IS_RSTREGARSTREG_INVERTED = 1'b0;
parameter IS_RSTREGB_INVERTED = 1'b0;
(* abc9_arrival=2454 *)
output [15:0] DOADO;
(* abc9_arrival=2454 *)
output [15:0] DOBDO;
(* abc9_arrival=2454 *)
output [1:0] DOPADOP;
(* abc9_arrival=2454 *)
output [1:0] DOPBDOP;
(* clkbuf_sink *)
(* invertible_pin = "IS_CLKARDCLK_INVERTED" *)
@ -5452,9 +5456,13 @@ module RAMB36E1 (...);
parameter IS_RSTREGB_INVERTED = 1'b0;
output CASCADEOUTA;
output CASCADEOUTB;
(* abc9_arrival=2454 *)
output [31:0] DOADO;
(* abc9_arrival=2454 *)
output [31:0] DOBDO;
(* abc9_arrival=2454 *)
output [3:0] DOPADOP;
(* abc9_arrival=2454 *)
output [3:0] DOPBDOP;
output [7:0] ECCPARITY;
output [8:0] RDADDRECC;
@ -8527,6 +8535,18 @@ module BUFIO2FB (...);
input I;
endmodule
module BUFPLL (...);
parameter integer DIVIDE = 1;
parameter ENABLE_SYNC = "TRUE";
(* clkbuf_driver *)
output IOCLK;
output LOCK;
output SERDESSTROBE;
input GCLK;
input LOCKED;
input PLLIN;
endmodule
module BUFPLL_MCB (...);
parameter integer DIVIDE = 2;
parameter LOCK_SRC = "LOCK_TO_0";