1270 commits

Author	SHA1	Message	Date
Clifford Wolf	92e4b5aa77	Add writeback mode to "sim" command	2017-08-17 15:54:51 +02:00
Clifford Wolf	7b4f3f86c3	Improve "sim" command	2017-08-17 12:27:08 +02:00
Clifford Wolf	75046aa531	Add "sim" command skeleton	2017-08-16 13:05:21 +02:00
Clifford Wolf	88983f5012	Mostly coding style related fixes in rmports pass	2017-08-15 11:32:35 +02:00
Clifford Wolf	9fe6bc48a9	Merge branch 'rmports' of https://github.com/azonenberg/yosys into azonenberg-rmports	2017-08-15 11:19:55 +02:00
Robert Ou	9a64ba3338	abc: Allow +/ filenames in the abc command	2017-08-14 12:11:11 -07:00
Andrew Zonenberg	15e41d6363	rmports: Now remove ports from cell instances if we optimized them out of that cell	2017-08-14 11:44:05 -07:00
Andrew Zonenberg	0ee27d0226	ProcessModule is no longer virtual (why was it in the first place?)	2017-08-14 11:18:09 -07:00
Andrew Zonenberg	bd2ac68769	rmports now works on all modules in the design, not just the top.	2017-08-14 11:16:44 -07:00
Andrew Zonenberg	d5e5bbad86	Updated Makefile to reflect opt_rmports being renamed to rmports	2017-08-14 11:04:56 -07:00
Andrew Zonenberg	1a6a23f91a	Renamed opt_rmports pass to rmports	2017-08-14 11:00:45 -07:00
Andrew Zonenberg	1bb150c231	Improved handling of constant connections in opt_rmports	2017-08-14 10:28:19 -07:00
Andrew Zonenberg	2877d5e504	Fixed handling of cell ports that aren't wires	2017-08-14 10:28:16 -07:00
Andrew Zonenberg	3dd7f42e2b	opt_rmports: Fixed incorrect handling of multi-bit nets	2017-08-14 10:28:11 -07:00
Andrew Zonenberg	66aac06eee	Removed commented out debug code	2017-08-14 10:28:04 -07:00
Andrew Zonenberg	cca3cb5fbb	Added opt_rmports pass (remove unconnected ports from top-level modules)	2017-08-14 10:27:59 -07:00
Clifford Wolf	007f29b9c2	Add support for set-reset cell variants to opt_rmdff	2017-08-09 13:29:52 +02:00
Clifford Wolf	c4a7958f70	Add handling of constant reset signals to opt_rmdff	2017-08-06 13:27:18 +02:00
Clifford Wolf	5c09f24e48	Fix typo in "abc" pass help message	2017-07-29 16:21:58 +02:00
Clifford Wolf	e7d1277a2c	Add consolidation of init attributes to opt_clean, some opt_clean log fixes	2017-07-29 00:10:33 +02:00
Clifford Wolf	649bb9374f	Add "opt_expr -fine" feature to remove neutral bits from reduce and logic operators	2017-07-26 18:28:55 +02:00
Clifford Wolf	b6bd12fade	Add error for cell output ports that are connected to constants	2017-07-22 15:08:30 +02:00
Clifford Wolf	b3bc7068d1	Fix handling of empty cell port assignments (i.e. ignore them)	2017-07-21 19:32:31 +02:00
Clifford Wolf	c00d8a5b73	Add $alu to list of supported cells for "stat -width"	2017-07-14 11:32:49 +02:00
Salvador E. Tropea	ca23554528	Excluded $_TBUF_ from opt_merge pass	2017-07-03 13:21:20 -03:00
Clifford Wolf	0a02cdb93b	Fix and_or_buffer optimization in opt_expr for signed operators	2017-07-01 16:05:26 +02:00
Clifford Wolf	0f217080cf	Add "design -import"	2017-06-30 19:18:52 +02:00
Clifford Wolf	8952bd6f45	Add chtype command	2017-06-30 17:57:34 +02:00
Clifford Wolf	18c030a8c9	Add $tribuf to opt_merge blacklist	2017-06-30 17:44:44 +02:00
Clifford Wolf	155a80dfb7	Fix handling of init values in "abc -dff" and "abc -clk"	2017-06-20 15:32:23 +02:00
Clifford Wolf	f6421c83a2	Switched abc "clock domain not found" error to log_cmd_error()	2017-06-20 04:22:34 +02:00
Clifford Wolf	05df3dbee4	Add "setundef -anyseq"	2017-05-28 11:59:05 +02:00
Clifford Wolf	9ed4c9d710	Improve write_aiger handling of unconnected nets and constants	2017-05-28 11:31:35 +02:00
Clifford Wolf	fad52abf70	Add aliases for common sets of gate types to "abc -g"	2017-05-24 11:39:05 +02:00
Clifford Wolf	05cdd58c8d	Add $_ANDNOT_ and $_ORNOT_ gates	2017-05-17 09:08:29 +02:00
Clifford Wolf	3bbac5c141	Fix equiv_simple, old behavior now available with "equiv_simple -short"	2017-04-28 18:57:53 +02:00
Larry Doolittle	2021ddecb3	Squelch trailing whitespace	2017-04-12 15:11:09 +02:00
Clifford Wolf	dee4ec1661	Fix gcc compiler warning	2017-04-05 11:21:06 +02:00
Clifford Wolf	180d704568	Disable opt_merge for $anyseq and $anyconst	2017-02-28 22:17:00 +01:00
Clifford Wolf	1a6c02a532	Add "chformal -assert2assume" and friends	2017-02-28 00:00:44 +01:00
Clifford Wolf	db7fc0e32d	Add "chformal" pass	2017-02-27 13:25:28 +01:00
Clifford Wolf	5f1d0b1024	Add $live and $fair cell types, add support for s_eventually keyword	2017-02-25 10:36:39 +01:00
Clifford Wolf	cf25dc9ce7	Copy attributes to _TECHMAP_REPLACE_ cells	2017-02-16 12:28:42 +01:00
Clifford Wolf	69468d5a16	Do not fix port widths on any blackbox instances	2017-02-13 17:07:38 +01:00
Clifford Wolf	db7314bc02	Fix techmap for inout ports connected to inout ports	2017-02-13 16:55:25 +01:00
Clifford Wolf	76c4ee096b	Do not eagerly fix port widths on parameterized cells	2017-02-12 17:42:57 +01:00
Clifford Wolf	95dae6d416	Fixed some "used uninitialized" warnings in opt_expr	2017-02-11 10:50:48 +01:00
Clifford Wolf	a5bfeb9e07	Add optimization of (a && 1'b1) and (a || 1'b0)	2017-02-11 10:05:00 +01:00
C-Elegans	94b272077d	Fix issue #306, "Bug in opt -full" ... Add check for whether the high bit in the constant expression is greater than the width of the variable, and optimizes that to a constant 1 or 0	2017-02-10 10:38:02 -05:00
Clifford Wolf	e6cc67b46f	Fix handling of init attributes with strange width	2017-02-09 16:06:58 +01:00