This website requires JavaScript.
Explore
Help
Register
Sign In
mirrors
/
yosys
Watch
3
Star
0
Fork
You've already forked yosys
0
mirror of
https://github.com/YosysHQ/yosys
synced
2025-04-06 01:24:10 +00:00
Code
Activity
9ed4c9d710
yosys
/
passes
History
Clifford Wolf
9ed4c9d710
Improve write_aiger handling of unconnected nets and constants
2017-05-28 11:31:35 +02:00
..
cmds
Improve write_aiger handling of unconnected nets and constants
2017-05-28 11:31:35 +02:00
equiv
Fix equiv_simple, old behavior now available with "equiv_simple -short"
2017-04-28 18:57:53 +02:00
fsm
Squelch trailing whitespace
2017-04-12 15:11:09 +02:00
hierarchy
Add $live and $fair cell types, add support for s_eventually keyword
2017-02-25 10:36:39 +01:00
memory
Typo fix.
2016-09-08 10:57:16 +03:00
opt
Squelch trailing whitespace
2017-04-12 15:11:09 +02:00
proc
Added $global_clock verilog syntax support for creating $ff cells
2016-10-14 12:33:56 +02:00
sat
Bugfix in "miter -assert" handling of assumptions
2016-10-17 14:56:58 +02:00
techmap
Add aliases for common sets of gate types to "abc -g"
2017-05-24 11:39:05 +02:00
tests
Add $live and $fair cell types, add support for s_eventually keyword
2017-02-25 10:36:39 +01:00