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Squelch trailing whitespace

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Larry Doolittle 2017-04-08 20:54:31 -07:00 • committed by Clifford Wolf
parent 41d4e91f38
commit 2021ddecb3
19 changed files with 165 additions and 165 deletions
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2
passes/equiv/equiv_purge.cc
View file

@ -142,7 +142,7 @@ struct EquivPurgeWorker
for (auto bit : queue)
visited.insert(bit);
for (auto bit : queue)
{
auto &cells = up_bit2cells[bit];

4
passes/fsm/fsm_detect.cc
View file

@ -180,7 +180,7 @@ static void detect_fsm(RTLIL::Wire *wire)
for (auto &port_it : cell->connections())
if (cell->output(port_it.first)) {
SigSpec sig = assign_map(port_it.second);
Const val(set_output ? State::S1 : State::S0, GetSize(sig));
Const val(set_output ? State::S1 : State::S0, GetSize(sig));
ce.set(sig, val);
}
}
@ -215,7 +215,7 @@ static void detect_fsm(RTLIL::Wire *wire)
for (auto w : warnings) warnmsg += " " + w;
log_warning("%s", warnmsg.c_str());
} else {
log("FSM state register %s.%s already has fsm_encoding attribute.\n", log_id(wire->module), log_id(wire));
log("FSM state register %s.%s already has fsm_encoding attribute.\n", log_id(wire->module), log_id(wire));
}
}
else

6
passes/opt/opt_expr.cc
View file

@ -1217,7 +1217,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
//references the constant signal in the comparison
RTLIL::SigSpec sigConst;
// note that this signal must be constant for the optimization
// note that this signal must be constant for the optimization
// to take place, but it is not checked beforehand.
// If new passes are added, this signal must be checked for const-ness
@ -1307,10 +1307,10 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
RTLIL::SigSpec a_prime(RTLIL::State::S0, 1);
if(is_lt){
a_prime[0] = RTLIL::State::S1;
log("Replacing %s cell `%s' (implementing unsigned X[%d:0] < %s[%d:0]) with constant 0.\n", log_id(cell->type), log_id(cell), width-1, log_signal(sigConst),const_width-1);
log("Replacing %s cell `%s' (implementing unsigned X[%d:0] < %s[%d:0]) with constant 0.\n", log_id(cell->type), log_id(cell), width-1, log_signal(sigConst),const_width-1);
}
else{
log("Replacing %s cell `%s' (implementing unsigned X[%d:0]>= %s[%d:0]) with constant 1.\n", log_id(cell->type), log_id(cell), width-1, log_signal(sigConst),const_width-1);
log("Replacing %s cell `%s' (implementing unsigned X[%d:0]>= %s[%d:0]) with constant 1.\n", log_id(cell->type), log_id(cell), width-1, log_signal(sigConst),const_width-1);
}
module->connect(cell->getPort("\\Y"), a_prime);
module->remove(cell);

2
passes/techmap/nlutmap.cc
View file

@ -92,7 +92,7 @@ struct NlutmapWorker
for (auto bit : sigmap(conn.second))
bit_lut_count[bit]++;
}
for (auto &cand : candidate_ratings)
{
for (auto &conn : cand.first->connections())