mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-28 03:15:50 +00:00
Code Activity

Do not eagerly fix port widths on parameterized cells

Browse source
This commit is contained in:
Clifford Wolf 2017-02-12 17:42:57 +01:00
parent 828303791b
commit 76c4ee096b
1 changed files with 3 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

3
passes/hierarchy/hierarchy.cc
View file

@ -625,6 +625,9 @@ struct HierarchyPass : public Pass {
for (auto module : design->modules())
for (auto cell : module->cells())
{
if (GetSize(cell->parameters) != 0)
continue;
Module *m = design->module(cell->type);
if (m == nullptr)