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Code Activity
17649 commits 143 branches 70 tags 52 MiB
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550 commits

Author SHA1 Message Date
Emil J. Tywoniak
0f884b6cba twine: avoid TwinePool::lookup 2026-07-20 12:27:18 +02:00
Emil J. Tywoniak
a9a190f70f twine: GC again WIP 2026-07-20 12:27:17 +02:00
Emil J. Tywoniak
c8e42bc15b twine: fix another off-by-one 2026-07-20 12:27:17 +02:00
Emil J. Tywoniak
94f347a71c twine: fix off-by-one static twine error 2026-07-20 12:27:17 +02:00
Emil J. Tywoniak
a5248849d9 WIP 2026-07-20 12:27:17 +02:00
Emil J. Tywoniak
b01a3694f0 WIP 2026-07-20 12:27:17 +02:00
Emil J. Tywoniak
77ad54139e WIP 2026-07-20 12:27:17 +02:00
Emil J. Tywoniak
e952044215 WIP 2026-07-20 12:27:17 +02:00
Emil J. Tywoniak
7422b71802 WIP 2026-07-20 12:27:17 +02:00
Emil J. Tywoniak
1210d8e117 WIP 2026-07-20 12:27:02 +02:00
Emil J. Tywoniak
30bc1c23ee WIP 2026-07-20 12:27:02 +02:00
Emil J. Tywoniak
10436f31cd WIP 2026-07-20 12:27:02 +02:00
Emil J. Tywoniak
f508244f36 rtlil: fix masquerade 2026-07-20 12:26:39 +02:00
Emil J. Tywoniak
edb43b93d7 rtlil: introduce ModuleNameMasq (KNOWN BROKEN, do not merge) 2026-07-20 12:26:39 +02:00
Emil J. Tywoniak
3da81b2e9d rtlil: Module::clone attaches to source design; callers use clone(dst) 2026-07-20 12:26:39 +02:00
Emil J. Tywoniak
be4d67d1a3 rtlil: replace AttrObject::meta_idx_ with ObjMeta pointer 2026-07-20 12:26:39 +02:00
Emil J. Tywoniak
84c6c61736 rtlil: extend per-Design meta vector to hold name slot 2026-07-20 12:26:39 +02:00
Emil J. Tywoniak
d7f88dd3a0 rtlil: evacuate src_id_ from AttrObject to per-Design meta vector 2026-07-20 12:26:39 +02:00
Emil J. Tywoniak
0bff07d55c rtlil: add Module* back-pointer to RTLIL::Memory 2026-07-20 12:26:39 +02:00
Emil J. Tywoniak
d37581d9d7 rtlil: add per-Design src meta vector + freelist 2026-07-20 12:26:39 +02:00
Emil J. Tywoniak
452964e75a rtlil: add Module* back-pointer to inner-process AttrObjects 2026-07-20 12:26:39 +02:00
Emil J. Tywoniak
f017bb8a93 twine 2026-07-20 12:26:39 +02:00
Emil J. Tywoniak
fd67ce2b80 WIP 2026-07-17 23:48:54 +02:00
Emil J. Tywoniak
07d5115135 patch: source transfer 2026-07-17 23:48:06 +02:00
Emil J. Tywoniak
e331300c58 patch: fix patch mixins 2026-07-17 23:48:00 +02:00
Emil J. Tywoniak
277b6f47dc rtlil: add CellAdderMixin for shared Cell adder interface between Module and Patch 2026-07-17 23:48:00 +02:00
Emil J. Tywoniak
20b0a9934b rtlil: allow friends to use Cell constructors with a factory token pattern 2026-07-17 23:47:08 +02:00
Emil J. Tywoniak
360527af1a rtlil: fix cloneInto in signorm 2026-07-17 23:33:03 +02:00
Emil J. Tywoniak
2fc93aa711 rtlil: sigNormalize Module when added to Design in signorm mode 2026-07-17 23:33:03 +02:00
Jannis Harder
b84beb598f WIP half broken snapshot 2026-07-17 23:32:20 +02:00
Michael Baier
5cd9efefe3 Adding widht checks to backend 2026-07-09 14:34:56 +02:00
nella
c99a037c33
Merge pull request #5886 from YosysHQ/nella/fix-signedness-5745 
Fix  `chparam` values are unsigned when using read_verilog frontend
 2026-06-18 16:50:22 +00:00
Miodrag Milanovic
8bbc3c359c Remove id2cstr uses in our code base 2026-05-16 19:49:45 +02:00
nella
7d3e56523b Preserve param signedness across overrides. 2026-05-13 16:25:15 +02:00
Codexplorer
e41b969da2 Refactored uses of log_id() 2026-05-08 20:59:24 -07:00
Emil J. Tywoniak
25b9b796c4 rtlil: complicate extract again for packing 2026-04-24 11:04:19 +02:00
Emil J. Tywoniak
14b0efeced rtlil: simplify extract for performance 2026-04-23 13:58:20 +02:00
Emil J. Tywoniak
ea11453cef rtlil: faster remove2 2026-03-18 23:33:35 +01:00
Robert O'Callahan
b42bb05b63 Parallelize Design::check() 2026-03-06 02:03:21 +00:00
Robert O'Callahan
e2166c4684 Parallelize collect_garbage() 2026-03-06 02:03:21 +00:00
nella
04822c6660 Readd builtin_ff_cell_types for plugin parity. 2026-03-04 12:39:45 +01:00
nella
66bd4716cf rtlil use newcelltypes. 2026-03-04 12:39:45 +01:00
Emil J. Tywoniak
ecb8b20f62 yosys: use newcelltypes for yosys_celltypes users 2026-03-04 12:39:44 +01:00
Emil J. Tywoniak
3212dfaf1f newcelltypes: fix unit test 2026-03-04 12:22:14 +01:00
Robert O'Callahan
dcd7742d52 Avoid scanning entire module if there are no wires to remove 
It's pretty common for `opt_clean` to find no wires to remove. In that case,
there is no point scanning the entire design, which can be significantly
expensive for huge designs.
 2026-01-23 01:38:20 +00:00
Robert O'Callahan
2c0448a81b Avoid spurious copy in IdStringCollector::trace_named() 2026-01-21 03:31:56 +00:00
nella
210b733555 Add rtlil string getters 2026-01-14 15:37:18 +01:00
Emil J
0ab967b036
Merge pull request #5564 from rocallahan/pass-fuzz 
Add support for fuzz-test comparison of two passes intended to give identical RTLIL results
 2026-01-06 20:07:31 +01:00
Robert O'Callahan
46cb05c471 Pass IdString by value instead of by const reference. 
When IdString refcounting was expensive, it made sense to pass it by const reference
instead of by value, to avoid refcount churn. Now that IdString is not refcounted,
it's slightly more efficient to pass it by value.
 2025-12-22 01:52:59 +00:00
Robert O'Callahan
ddd6a16ee0 Add -legalize option to read_rtlil 2025-12-21 21:47:48 +00:00