mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-31 11:42:30 +00:00
Code Activity
6718 commits 122 branches 59 tags 73 MiB
Commit graph

599 commits

Author SHA1 Message Date
SergeyDegtyar
eb0a5b2293 Remove unnecessary common.v(assertions for testbenches). 2019-08-30 09:17:32 +03:00
SergeyDegtyar
8e3abda193 Remove simulation from run-test.sh (unnecessary paths) 2019-08-30 09:11:03 +03:00
SergeyDegtyar
20f4aea480 Remove simulation from run-test.sh 2019-08-30 08:53:35 +03:00
Sergey
d360693040
Merge pull request #3 from YosysHQ/Sergey/tests_ice40 
Merge my changes to tests_ice40 branch
 2019-08-29 21:07:34 +03:00
SergeyDegtyar
d588c6898f Add comments for examples from Lattice user guide 2019-08-29 10:49:46 +03:00
Eddie Hung
b8a9f73089 Comment out *.sh used for testbenches as we have no more 2019-08-28 12:36:20 -07:00
Eddie Hung
87d5d9b8c8 Use equiv for memory and dpram 2019-08-28 12:30:35 -07:00
Eddie Hung
ebd0a1875b Use equiv_opt for latches 2019-08-28 12:21:15 -07:00
Eddie Hung
32eef26ee2 Merge remote-tracking branch 'origin/clifford/async2synclatch' into Sergey/tests_ice40 2019-08-28 12:18:32 -07:00
SergeyDegtyar
fe58790f37 Revert "Add tests for ecp5" 
This reverts commit 2270ead09f.
 2019-08-28 09:49:58 +03:00
SergeyDegtyar
2270ead09f Add tests for ecp5 2019-08-28 09:47:03 +03:00
Clifford Wolf
70c0cddb1e
Merge pull request #1325 from YosysHQ/eddie/sat_init 
In sat: 'x' in init attr should be ignored
 2019-08-28 00:18:14 +02:00
Eddie Hung
00387f3927 Revert to using clean 2019-08-27 09:24:32 -07:00
SergeyDegtyar
980830f7b8 Revert "Add tests for ecp5 architecture." 
This reverts commit 134d3fea90.
 2019-08-27 18:28:05 +03:00
Marcin Kościelnicki
5fb4b12cb5 improve clkbuf_inhibit propagation upwards through hierarchy 2019-08-27 17:26:47 +02:00
SergeyDegtyar
134d3fea90 Add tests for ecp5 architecture. 2019-08-27 18:12:18 +03:00
SergeyDegtyar
aad9bad326 Add tests for macc and rom; 
Test cases from
https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071;
In both cases synthesized only LUTs and DFFs.
 2019-08-27 13:56:26 +03:00
Eddie Hung
528f1c8687 Improve tests to check that clkbuf is connected to expected 2019-08-26 13:45:16 -07:00
Eddie Hung
dc87372a97 Wire with init on FF part, 1'bx on non-FF part 2019-08-24 15:05:44 -07:00
Eddie Hung
a0d85393e3 Check clkbuf_inhibit=1 is ignored for custom selection 2019-08-23 11:15:26 -07:00
Eddie Hung
5628e2ec53 Add simple clkbufmap tests 2019-08-23 11:10:02 -07:00
Eddie Hung
d62c10d641 tests/techmap/run-test.sh to cope with *.ys 2019-08-23 11:09:50 -07:00
Eddie Hung
10c41a5cf5 Blocking assignment 2019-08-23 09:11:04 -07:00
SergeyDegtyar
c29380b381 Fix pull request 2019-08-23 18:55:01 +03:00
SergeyDegtyar
3c10f58d04 Fix run-test.sh; Add new test for dpram. 2019-08-23 17:00:16 +03:00
SergeyDegtyar
0b25dbf1c6 Fix path in run-test.sh 2019-08-23 12:40:14 +03:00
Eddie Hung
fe1b2337fd Do not propagate mem2reg attribute through to result 2019-08-22 16:57:59 -07:00
Eddie Hung
36cf0a3dd5 Remove adffs_tb.v 2019-08-22 16:50:14 -07:00
Eddie Hung
51ffb093b5 In sat: 'x' in init attr should not override constant 2019-08-22 16:43:08 -07:00
Eddie Hung
698a0e3aaf WIP for equivalency checking memories 2019-08-22 16:05:12 -07:00
Eddie Hung
43e7c4917a Do not print OKAY 2019-08-22 16:05:12 -07:00
Eddie Hung
5061d239ae Fail if iverilog fails 2019-08-22 16:05:12 -07:00
Eddie Hung
8e3754bdb4 Hide tri-state warning message for now 2019-08-22 16:05:12 -07:00
Eddie Hung
659a481482 Remove unused output 2019-08-22 16:05:12 -07:00
Eddie Hung
61087329ef Fix tribuf test 2019-08-22 16:05:12 -07:00
Eddie Hung
f9906eed68 Fix comments 2019-08-22 16:05:12 -07:00
Eddie Hung
9224b3bc17 Remove tech independent synthesis 2019-08-22 16:05:12 -07:00
Eddie Hung
388eb3288c Remove dffe instantation 2019-08-22 16:04:50 -07:00
Eddie Hung
9e537a76b5 Move $dffe to dffs.{v,ys} 2019-08-22 16:04:48 -07:00
Eddie Hung
c5754d9e8b Make multiplier wider, do not do tech independent synth 2019-08-22 16:04:07 -07:00
Eddie Hung
b800059fc1
Merge pull request #1317 from YosysHQ/eddie/opt_expr_shiftx 
opt_expr to trim A port of $shiftx/$shift
 2019-08-22 10:31:27 -07:00
Eddie Hung
6f971470f8 Respect opt_expr -keepdc as per @cliffordwolf 2019-08-22 08:37:27 -07:00
Eddie Hung
379f33af54 Handle $shift and Y_WIDTH > 1 as per @cliffordwolf 2019-08-22 08:22:23 -07:00
Eddie Hung
bb1a8a0190 Add test 2019-08-21 21:58:20 -07:00
Eddie Hung
a6776ee35e mem2reg to preserve user attributes and src 2019-08-21 13:36:01 -07:00
SergeyDegtyar
d945b8a357 Fix all comments from PR 2019-08-21 21:52:07 +03:00
SergeyDegtyar
b835ec37cb Add temp directory 2019-08-21 07:53:34 +03:00
Eddie Hung
fce8dc7db2 Add test 2019-08-20 20:05:16 -07:00
SergeyDegtyar
71dd412ac5 Fix tests; Remove simulation; 
- Add -map and -assert options for equiv_opt;
	!!! '-assert' option was commented for the next tests (unproven
$equiv cells was found):
		- dffs;
		- div_mod;
		- latches;
		- mul_pow;
- Add design -load;
- Remove simulations;
 2019-08-20 15:52:25 +03:00
Clifford Wolf
d0117d7d12
Merge branch 'master' into clifford/pmgen 2019-08-20 11:39:23 +02:00